Non-Volatile Memory ECC Layout for High Bit Error Rates
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Solution Overview
Problem
Memory systems using non-volatile memory, such as NAND flash, face errors due to time lapse and noise during reading and writing, necessitating effective error correction mechanisms to ensure data integrity.
Innovation Solution
A memory system employing a multi-dimensional error correction code with non-uniform configuration of component codes and shared bits, where different component codes have varying error correction capabilities and protection ratios, enhancing the overall error correction capability by optimizing the distribution of shared bits and protection across symbol groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform error correction code configuration is used, then the system structure is simple, but the error correction capability is insufficient for handling high bit error rates
Solution Approach 1:
The patent applies local quality by configuring different component codes with different error correction capabilities in different regions of the code structure. Specifically, it uses multiple component codes (first through fourth component codes) with varying correction capabilities, and strategically places them to protect different symbol groups based on their error correction needs. This allows the system to provide stronger protection where needed while maintaining overall code efficiency.
Solution Approach 2:
The patent implements asymmetry by creating a non-uniform distribution of shared bits between component codes. The first symbol group has a different ratio of symbols protected by the third component code compared to the second symbol group. This asymmetric configuration optimizes error correction for specific patterns of bit errors that are more likely to occur in non-volatile memory, thereby improving overall reliability without requiring complete uniformity across all code positions.
2Reliability
If more shared bits are used between component codes, then error correction capability improves, but decoding complexity and processing time increase
Solution Approach 1:
The patent segments the error correction code into multiple component codes (first, second, third, and fourth component codes) that can be decoded independently or in combination. Each component code handles specific symbol groups, allowing the decoding process to be divided into manageable stages. This segmentation enables the system to achieve high error correction capability while controlling decoding complexity by processing different code segments separately rather than as a monolithic block.
Solution Approach 2:
The patent applies partial action by using different ratios of shared bits for different symbol groups rather than uniformly applying maximum shared bits across all groups. The first symbol group uses a first ratio of symbols protected by the third component code, while the second symbol group uses a second ratio. This selective application of error correction resources achieves sufficient protection for the most error-prone regions without unnecessarily increasing decoding complexity for all regions.
3Duration of action of stationary object
If non-volatile memory is used for data storage, then data retention is improved, but errors due to time lapse and noise increase
Solution Approach 1:
The patent applies beforehand cushioning by incorporating multiple layers of error correction codes with different capabilities during the data encoding phase. The multi-dimensional error correction code structure with multiple component codes and shared bits is prepared in advance to cushion against the accumulation of errors that occur during long-term storage and repeated read/write operations. This proactive error protection allows the system to maintain data integrity even after extended periods of storage and multiple access cycles.
Data Source
AI summary
A memory system of an embodiment includes a non-volatile memory and a memory controller. The memory controller generates an error correction code including a first and second symbol groups. The first symbol group is a set of symbols shared between a first component code and a third component code and/or a fourth component code. The second symbol group is a set of symbols shared between a second component code and the third component code and/or the fourth component code. The first and third component codes have a lower correction capability than the second and fourth component codes, respectively. The ratio of symbols protected by the third component code is smaller in the second symbol group than in the first symbol group. The ratio of symbols protected by the fourth component code is larger in the second symbol group than in the first symbol group.