Memory ECC Bit Poisoning for On-Die and Host Validation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices scale to increase memory densities, ensuring reliability becomes challenging due to the difficulty in testing and validating the functionality of error correcting code (ECC) circuits, both on-die and system-level, especially after deployment in systems where access to test modes is limited.
Innovation Solution
The implementation of a method to 'poison' data bits within memory devices, allowing host devices to control which bits to invert during write or read operations, enabling the testing of ECC circuit functionality by generating and correcting errors, thereby validating the ECC circuit's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices scale to increase memory densities, then storage capacity is improved, but reliability becomes more difficult to ensure due to ECC circuit testing challenges
Solution Approach 1:
The patent applies preliminary action by enabling ECC circuit testing to be performed before memory devices are deployed into final systems. The test mode allows ECC functionality to be validated in advance during manufacturing or assembly, rather than attempting to test after deployment when access is limited. This resolves the contradiction by shifting the testing action to an earlier time when full access is available, thereby ensuring reliability without sacrificing memory density scaling.
Solution Approach 2:
The patent implements self-service by enabling the memory device to test its own ECC circuits through built-in test mode functionality. The device can generate test patterns, perform ECC encoding/decoding operations, and validate error detection and correction capabilities internally without requiring external testing equipment. This self-testing capability ensures ECC reliability while allowing continuous memory density improvements, as the testing is integrated into the device itself rather than requiring separate external test infrastructure.
2Reliability
If test modes are used to validate ECC circuits, then reliability is improved, but access to test modes is limited after deployment
Solution Approach 1:
The patent applies preliminary action by performing comprehensive ECC validation during manufacturing or assembly when test mode access is easily available. All necessary testing of error detection and correction functionality is completed before the device is deployed into its final system. This resolves the contradiction by ensuring reliability is established in advance, eliminating the need for post-deployment test mode access.
Solution Approach 2:
The patent implements self-service by enabling the memory device to autonomously test and validate its own ECC circuits through integrated self-test functionality. The device can execute test patterns, perform encoding/decoding operations, and verify error correction capabilities without requiring external testing equipment or special access conditions. This self-testing capability maintains ease of operation even after deployment, as the device can validate its own ECC functionality through normal operational interfaces rather than requiring specialized test mode access.
3Reliability
If ECC circuits are integrated into memory devices, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the ECC circuits directly into the memory device architecture, combining error detection and correction functionality with the memory array and control logic. The ECC encoder, decoder, and associated circuitry are merged with the memory structure to provide unified error protection. This resolves the contradiction by achieving high data integrity through tight integration, where the ECC functionality becomes an inherent part of the memory device rather than a separate add-on, thereby managing complexity through consolidation.
Solution Approach 2:
The patent implements universality by designing the ECC circuits to handle multiple error types and correction scenarios within a single integrated structure. The same ECC circuitry performs both error detection and correction functions, and can operate in different modes (test mode and normal operation mode) depending on the situation. This multi-functionality reduces overall device complexity by using a single versatile ECC subsystem rather than separate dedicated circuits for each function, while maintaining high data integrity through comprehensive error handling capabilities.
Data Source
AI summary
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to poison data based on an indication provided by a host device coupled with the memory devices. The indication may include which one or more bits to poison (invert) at which stages of performing write or read operations. In some embodiments, the memory device may invert one or more bits according to the indication and then correct one or more errors associated with inverting the one or more bit to verify its on-die ECC functionality. In some embodiments, the memory device may provide the host device with poisoned data including one or more bits inverted according to the indication such that the host device may test system-level ECC functionality using the poisoned data.