Memory ECC Bit Reclamation for Error-Tolerant Data Formats
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Solution Overview
Problem
Modern memory systems face inefficiencies in error correction due to fixed widths for data and ECC bits, leading to varying levels of data integrity that can result in catastrophic failures or negligible errors, especially in systems with mixed criticality like CPUs and AI coprocessors.
Innovation Solution
ECC bits are reclaimed and reallocated based on fault tolerance, allowing for selective protection of data bits and conditional disablement of ECC, with ECC logic circuitry strategically placed within the computing system to improve accuracy and throughput by aggregating data transmissions and reallocating ECC bits as data bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed width ECC bits are used according to standard memory protocols, then error detection and correction capability is maintained, but data transmission efficiency and throughput are reduced due to redundant bits
Solution Approach 1:
The patent implements dynamic ECC configuration where the number of ECC bits is adjusted based on the actual fault tolerance requirements of the data being transmitted. Instead of using a fixed number of ECC bits for all data transmissions, the system dynamically determines the appropriate ECC bit count by analyzing the error detection and correction needs of specific data patterns, thereby optimizing the balance between reliability and transmission efficiency.
Solution Approach 2:
The system changes the parameter of ECC bit quantity from a fixed standard value to a variable value that adapts to different data transmission scenarios. By modifying the number of ECC bits based on actual error rates and data criticality, the system achieves better transmission efficiency while maintaining adequate error protection where needed.
2Reliability
If more ECC bits are allocated to all data transmissions, then error correction capability is improved, but system throughput and precision are reduced due to increased redundancy
Solution Approach 1:
The patent applies different levels of ECC protection to different portions of data based on their specific error tolerance requirements. Critical data fields receive stronger ECC protection while less critical fields use reduced or no ECC, creating a localized quality approach where protection intensity varies by data region rather than applying uniform protection across all data.
Solution Approach 2:
Instead of applying full ECC protection to all data bits, the system applies partial ECC action only to the extent necessary for error correction. By using fewer ECC bits than the maximum available, the system achieves adequate error correction capability while avoiding the excessive redundancy that would degrade transmission precision and throughput.
3Adaptability or versatility
If standard memory protocols with fixed ECC widths are used, then system compatibility is maintained, but adaptability to different data formats and precision requirements is limited
Solution Approach 1:
The patent creates a universal ECC system that can handle multiple data formats and precision requirements through a single configurable framework. The ECC logic circuitry is designed to adapt to different data widths and error correction needs, making the same hardware capable of supporting various data transmission scenarios without requiring separate dedicated ECC systems for each format.
Data Source
AI summary
A method for operating a computing system includes determining a baseline accuracy of the computing system based on a baseline data transmission format comprising a baseline quantity of data bits and a baseline quantity of error correction (ECC) bits, determining sample accuracies of the computing system based on sample data transmission formats each including a quantity of data bits and a quantity of ECC bits that are different from the baseline quantity of data bits and the baseline quantity of ECC bits, and storing data in a memory device of the computing system using at least one data transmission format, wherein the at least one data transmission format is selected from a group of data transmission formats comprising the baseline data transmission format and the sample data transmission formats and the at least one data transmission is selected based on the baseline accuracy and the sample accuracies.


