Semiconductor Memory ECC Buffer for Multi-Write Reliability
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Solution Overview
Problem
Existing semiconductor devices lack efficient mechanisms for correcting errors in data storage operations, particularly in scenarios involving multiple write operations, which can lead to reduced data reliability and increased layout area requirements.
Innovation Solution
Incorporating an error correction buffer circuit and error correction signal storage circuit within the semiconductor device to generate and store error correction signals during write operations, allowing for improved data reliability by correcting errors in both first and second data storage blocks, and sharing the error correction signal storage across multiple data storage blocks to reduce layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction mechanisms are added to correct errors in multiple write operations, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error correction signal storage function into the existing data storage blocks. The data storage blocks are designed to store both data and error correction signals, eliminating the need for separate error correction storage circuits. This integration reduces device complexity while maintaining the capability to correct errors in multiple write operations across different channels.
Solution Approach 2:
The data storage blocks are given multi-functionality by enabling them to perform both data storage and error correction signal storage. This universal design allows the same hardware resources to serve multiple purposes: storing first channel data, second channel data, first error correction signals, and second error correction signals, thereby improving reliability without proportionally increasing device complexity.
2Reliability
If separate error correction storage circuits are added for each data storage block, then data reliability is improved, but layout area increases
Solution Approach 1:
The patent combines the error correction signal storage function with the data storage blocks, so that the same physical storage resources are used for both data and error correction signals. This merging eliminates the need for separate error correction storage circuits, thereby reducing the overall layout area while maintaining comprehensive error correction capability across multiple data storage blocks.
Solution Approach 2:
The data storage blocks are designed as universal storage units that can hold both data and error correction signals. This multi-functional design optimizes the use of storage resources and minimizes the required layout area by avoiding redundant storage circuits for error correction signals.
3Reliability
If error correction is implemented for multiple write operations, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error correction functionality into the data storage blocks themselves, allowing the same storage resources to handle both data and error correction signals for multiple write operations. This integration approach enables comprehensive error correction across first and second channels without proportionally increasing device complexity.
Solution Approach 2:
The data storage blocks are designed with universal functionality to handle multiple operations: storing first channel data, second channel data, generating first error correction signals, and generating second error correction signals. This multi-functional design simplifies the overall device architecture while maintaining robust error correction capabilities for multiple write operations.
Data Source
AI summary
A semiconductor device includes an error correction buffer circuit that generates an error correction signal when one of a first write operation and a second write operation is performed based on a command address, a first chip selection signal, a second chip selection signal, first data, and second data; a first data storage block that stores the first data when the first write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal, a second data storage block that stores the second data when the second write operation is performed based on the command address, the first chip selection signal, and the second chip selection signal; and an error correction signal storage circuit that stores the error correction signal when one of the first write operation and the second write operation is performed based on the command address.