Memory ECC Buffering to Postpone High-BER Refresh Operations

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Solution Overview

Problem

Existing memory systems face performance degradation due to prioritizing refresh operations under adverse conditions such as extreme temperatures, long power-off durations, or high bit-error-rates (BER) in a small percentage of word lines, leading to increased write amplification and latency.

Innovation Solution

Memory systems evaluate a range of BER thresholds to determine if refresh operations can be postponed, generating additional error correction code (ECC) bits for pages within these thresholds and storing them in a buffer until conditions are favorable for performing the refresh, thereby improving error correction capability and reducing adverse effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operations are prioritized under adverse conditions (extreme temperatures, long power-off durations, high BER), then data integrity is maintained, but write amplification and latency increase

Engineering Contradiction:
Improvedata integrityVSAvoidwrite amplification and latency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts the BER threshold parameter based on environmental conditions. Under adverse conditions (extreme temperatures, long power-off durations), the threshold is raised from the default value, allowing refresh operations to be postponed. This parameter change enables the system to tolerate higher BER temporarily, reducing unnecessary refresh operations and their associated write amplification and latency penalties.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The refresh operation prioritization is made dynamic rather than static. The system continuously monitors environmental conditions (temperature, power-off duration) and adjusts refresh timing accordingly. Under normal conditions, refresh operations are performed promptly to maintain data integrity. Under adverse conditions, the system dynamically postpones refresh operations, creating a flexible approach that balances data integrity with performance optimization.

Inventive Principle:
Principle #15Dynamics

2Reliability

If refresh operations are performed promptly to correct errors, then bit-error-rate is reduced, but system latency increases

Engineering Contradiction:
Improvebit-error-rateVSAvoidsystem latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system changes the BER threshold parameter dynamically based on environmental conditions. When temperature is extreme or power-off duration is long, the threshold is increased, allowing the system to tolerate higher BER temporarily without triggering immediate refresh operations. This reduces the frequency of refresh operations and their associated latency impact on normal read/write operations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system takes preliminary action by monitoring environmental conditions and adjusting the BER threshold before errors accumulate to critical levels. By proactively raising the threshold under adverse conditions, the system prevents unnecessary refresh operations from being triggered, thereby avoiding the latency penalty while still maintaining data integrity through conditional error correction.

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If additional ECC bits are generated for pages with BER within threshold range, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidECC generation and buffer management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of applying uniform error correction to all pages, the system applies additional ECC bits selectively only to pages whose BER falls within a specific threshold range. This local quality approach means that only certain pages receive enhanced error correction treatment, reducing the overall complexity compared to universally applying strong ECC to all data. The buffer management complexity is localized to handling only these specific pages requiring additional protection.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250391491A1Error correction configurations for memory systems
Publication Date: 2025.12.25 MICRON TECHNOLOGY INC
  • US20250391491A1 patent drawing
  • US20250391491A1 patent drawing
  • US20250391491A1 patent drawing

AI summary

Methods, systems, and devices for error correction configurations for memory systems are described. The described techniques provide for a memory system to evaluate one or more additional conditions when determining whether to initiate a refresh operation. For example, the memory system may determine whether the bit error rate (BER) of a page of memory cells satisfies a lower bound threshold corresponding to the BER threshold that triggers a refresh operation, and an upper bound threshold indicative of a BER at which a refresh operation may be prioritized. If the BER of a page is within the range of threshold values, the memory system may generate one or more additional layers of encoding associated with the page and may postpone the refresh operation for a duration.