Memory ECC Candidate Bit Analysis for Multi-Bit Error Correction
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Solution Overview
Problem
Current error-correcting code functionalities in memory devices are limited in detecting and correcting multiple erroneous bits, requiring larger components and additional storage for improved functionality, which increases the size of integrated circuits.
Innovation Solution
The method identifies and utilizes candidate bits within memory devices to enhance error correction capabilities, allowing for the detection and correction of more erroneous bits than standard error-correcting code functionalities, using a smaller error correcting module by evaluating bits to determine unreliable candidate bits and inverting them to achieve a non-error state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard error-correcting code functionality is used, then the memory device can detect and correct a limited number of erroneous bits, but the integrated circuit size increases due to larger components and additional storage requirements
Solution Approach 1:
The patent segments the error correction process into two distinct phases: (1) standard error-correcting code functionality that handles detectable and correctable errors, and (2) a candidate bit analysis phase that identifies and corrects additional erroneous bits beyond the standard capability. This segmentation allows the system to achieve enhanced error correction without requiring a completely redesigned error correction code structure, thereby limiting the increase in integrated circuit size while improving reliability.
Solution Approach 2:
The patent performs preliminary identification of candidate bits before final error correction. By analyzing bit reliability metrics and identifying candidate bits that are likely to be erroneous before the actual correction process, the system can efficiently target correction resources. This preliminary action enables the detection and correction of multiple erroneous bits without proportionally increasing the complexity of the error correction hardware.
2Reliability
If single error correcting and double error detecting functionality is used, then up to two erroneous bits can be detected and one can be corrected, but the system remains unable to correct more than one erroneous bit
Solution Approach 1:
The patent introduces a dynamic error correction capability that adapts to the actual error conditions in the data. Instead of being fixed at correcting only one error, the system dynamically identifies candidate bits through reliability analysis and can correct multiple erroneous bits when detected. This dynamic approach allows the error correction capability to flexibly adjust based on the number and distribution of errors in each specific data set, thereby improving both reliability and adaptability.
Data Source
AI summary
A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.