Memory ECC Layout for Shared Sub-Word Line Cell Groups
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Solution Overview
Problem
As memory device capacities increase, producing memory devices with no defective memory cells becomes increasingly difficult, necessitating improved error correction capabilities beyond traditional methods.
Innovation Solution
A memory device design that includes a memory core with cell groups sharing sub-word line drivers and an error correction circuit that corrects errors in units of symbols using a check matrix, expanding error correction capability to handle errors at both ends of adjacent symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing syndromes for all possible error patterns in a lookup table before actual memory operations. When an error occurs, the system can quickly retrieve the pre-compared syndrome to identify and correct the error, rather than performing complex real-time calculations. This prepares the error correction mechanism in advance, enabling reliable correction even as memory capacity and defect probability increase.
2Device complexity
If traditional error correction methods are used, then implementation simplicity is maintained, but error correction capability is insufficient for high-capacity memories
Solution Approach 1:
The patent segments the error correction process into distinct functional components: syndrome calculation units that compute syndromes from received data, a lookup table storing pre-calculated syndromes for various error patterns, and comparison units that match received syndromes against the lookup table. This segmentation allows each component to be optimized independently and facilitates parallel processing, improving error correction capability without overwhelming system complexity.
Solution Approach 2:
The patent introduces an intermediary lookup table that stores the relationship between syndromes and corresponding error patterns. This lookup table acts as a mediator between the syndrome calculation and error identification processes, translating complex syndrome data into actionable error correction information without requiring complex real-time computation, thus enhancing capability while managing complexity.
3Reliability
If error correction is performed in units of symbols, then correction capability is expanded, but processing complexity increases
Solution Approach 1:
The patent implements periodic action by processing errors in discrete symbol units rather than continuous streams. The error correction circuit is configured to calculate syndromes and perform corrections for fixed-size symbol blocks, allowing the system to reset and re synchronize after each symbol unit. This periodic processing structure makes the complexity manageable by breaking it into repeating, predictable cycles that can be efficiently implemented with standardized circuit blocks.
Data Source
AI summary
A memory device includes a memory core including a plurality of cell blocks grouped into a plurality of cell groups, each cell group including adjacent cell blocks disposed in a row direction and sharing sub-word line drivers with adjacent cell groups; and an error correction circuit configured to, during a read operation, correct an error of main data in units of symbols by calculating the main data and an error correction code, which are read from the memory core, with a check matrix, each unit of symbols including data output from one cell group, or data output from cell blocks disposed at both ends of two adjacent cell groups based on a sub-word line driver shared between the two adjacent cell groups.