Memory ECC Reconfiguration for Uneven Cell Retention

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Solution Overview

Problem

Conventional error correction codes in memory devices apply uniform intensity to all memory cells, which is inefficient as the stability of data stored in memory devices decreases over time due to aging and varying environmental conditions, leading to potential data loss and corruption.

Innovation Solution

A memory device with a reconfiguration logic unit that groups data based on the data retention properties of each memory cell, applying different error correction encoding and decoding algorithms with varying intensities to each group, ensuring that data stored in memory cells with weaker retention properties receive stronger error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uniform error correction intensity is applied to all memory cells, then implementation simplicity is maintained, but error correction efficiency deteriorates as memory cells age and exhibit varying stability

Engineering Contradiction:
Improveerror correction efficiencyVSAvoiderror correction implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different error correction intensities to different memory cell groups based on their individual stability characteristics. Memory cells are classified into multiple groups according to their data retention properties, and each group receives error correction processing with intensity matched to its specific needs, rather than applying uniform error correction to all cells.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The error correction intensity is dynamically adjusted based on the aging state and stability of memory cells. As memory cells degrade over time, their stability changes, and the system adapts by modifying the error correction intensity accordingly, making the error correction process responsive to the actual state of the memory cells rather than static.

Inventive Principle:
Principle #15Dynamics

2Reliability

If stronger error correction is applied to all memory cells, then data stability is improved, but processing overhead and resource consumption increase

Engineering Contradiction:
Improvedata stabilityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies stronger error correction only to memory cell groups that exhibit lower stability, while using lighter error correction for more stable cells. This localized approach ensures data stability for vulnerable cells without unnecessarily increasing processing overhead for all memory operations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system applies error correction intensity that is partially sufficient or slightly excessive for each memory cell group based on their stability characteristics. For unstable cells, stronger correction is applied to ensure reliability, while for stable cells, minimal correction is used to maintain processing efficiency.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If error correction intensity is increased for aged memory cells, then data retention is improved, but memory operation speed decreases

Engineering Contradiction:
Improvedata retentionVSAvoidmemory operation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent identifies memory cells with poor data retention through classification and applies enhanced error correction only to those specific cells. Memory cells that maintain good retention characteristics continue to operate with standard error correction, preserving their speed performance while ensuring reliability for degraded cells.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11119852B2Memory device having error correction function and error correction method for memory device
Publication Date: 2021.09.14 RES & BUSINESS FOUND SUNGKYUNKWAN UNIV
  • US11119852B2 patent drawing
  • US11119852B2 patent drawing
  • US11119852B2 patent drawing

AI summary

A memory device having an error correction function includes: a memory element including multiple memory cells, a reconfiguration logic unit configured to group input data according to data retention properties of each memory cell in which each of the input data will be stored or group storage data stored in the memory element according to data retention properties of each memory cell in which each of the storage data is stored and arrange each of the input data or each of the storage data grouped by identical retention properties to be adjacent to each other, an error correction encoder configured to apply an error correction encoding algorithm with a different intensity to the grouped input data in each group, and an error correction decoder configured to apply an error correction decoding algorithm corresponding to an intensity applied by the error correction encoder to the grouped storage data in each group.