Semiconductor Memory ECC Switching for Charge Leakage Errors
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Solution Overview
Problem
Nonvolatile semiconductor memory devices with laminated gate structures face data loss over time due to charge leakage, leading to errors, and existing high-error correction mechanisms consume excessive power and resources even for short data storage periods.
Innovation Solution
A semiconductor memory device with error correction circuits that generate detecting codes, first correcting codes for low-power correction of individual data blocks, and a second correcting code for larger blocks, optimizing error correction capability based on storage time to reduce power waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-performance error correction mechanism is used to guarantee correct information restoration after long storage, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the error correction mechanism adaptable rather than static. The control circuit dynamically selects between first and second error correction mechanisms based on the storage time of data. For recently written data, the simpler first mechanism is used, while for older data prone to charge leakage, the more robust second mechanism is activated. This dynamic adaptation resolves the contradiction by matching error correction strength to actual need, reducing unnecessary power consumption while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of error correction capability based on storage time. The control circuit monitors how long data has been stored and adjusts the error correction mechanism accordingly. When storage time exceeds a threshold indicating potential charge leakage issues, the system switches from the first error correction mechanism to the second, more capable mechanism. This parameter-based adaptation allows the system to optimize power consumption while ensuring error correction reliability when needed.
2Reliability
If a high-performance error correction mechanism is used for all data, then error correction capability is improved, but circuit scale increases
Solution Approach 1:
The patent segments the error correction functionality into two distinct mechanisms: a first error correction mechanism for recent data and a second error correction mechanism for older data. The control circuit divides the error correction task based on data age, activating only the appropriate mechanism for each data item. This segmentation allows the system to avoid deploying the full-power second mechanism for all data, thereby reducing overall circuit scale while maintaining high error correction capability when needed.
Solution Approach 2:
The system changes the error correction parameter based on data storage time. The control circuit evaluates the age of stored data and switches between two error correction mechanisms with different capabilities. For short-term storage where charge leakage is minimal, a simpler correction mechanism suffices. For long-term storage where errors are more likely, the more capable second mechanism is activated. This parameter-based switching optimizes circuit scale by avoiding unnecessary complexity for all data processing.
3Reliability
If a high-performance error correction mechanism is used for all data, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent implements dynamic error correction by having the control circuit adjust the correction mechanism based on data storage time. For recently written data that is less prone to errors, the faster first error correction mechanism is used, minimizing processing time. For older data where charge leakage may have caused errors, the system switches to the more thorough second error correction mechanism. This dynamic approach resolves the time contradiction by applying intensive correction only when necessary, rather than uniformly for all data.
Solution Approach 2:
The system changes the error correction parameter based on the storage time of data. The control circuit monitors data age and switches between two error correction mechanisms with different processing characteristics. When data has been stored for a long time and error probability increases, the system activates the more capable but slower second mechanism. For fresher data, the quicker first mechanism is used. This parameter-based adaptation optimizes processing time while maintaining error correction reliability when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power consumption and circuit scale while maintaining high error correction capability, adapting to varying error rates by using low-power Hamming codes for short-term data and high-capability codes like Reed-Solomon codes for long-term data, minimizing unnecessary power usage.
Implementation Method 1
electrons are injected from the substrate to the floating gate electrode through the tunnel insulating film
Implementation Method 2
The electric charges accumulated in the floating gate electrode leak to the substrate through the tunnel insulating film as the time elapses
Data Source
AI summary
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.