Memory ECC Check Matrix for Defect-Tolerant High-Capacity Arrays
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, leading to a need for error correction methods to address errors in memory systems.
Innovation Solution
A memory system incorporating an error correction code generation circuit and an error correction circuit that utilize a check matrix to generate and correct errors, with specific configurations for group indicators and bit indicators to minimize errors during data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The memory data is divided into multiple data groups (e.g., 8 data groups of 16 bits each), and error correction codes are generated for each group separately using distinct group indicators in the check matrix. This segmentation allows independent error detection and correction for each data group, improving overall reliability while maintaining high capacity.
Solution Approach 2:
Error correction code (ECC) circuits are introduced as intermediary components between the memory cells and the data processing units. These ECC circuits generate and utilize syndrome values based on check matrices with specific Hamming distance properties to detect and correct errors, thereby maintaining data integrity in high-capacity memory devices.
2Reliability
If error correction code generation is performed for each data group, then error detection capability is improved, but circuit complexity increases
Solution Approach 1:
A single error correction circuit is designed to handle multiple data groups universally. The circuit uses a check matrix with group indicators that can identify and process errors across different data groups (e.g., DQ0_Group to DQ7_Group) through a unified syndrome calculation mechanism, reducing the need for separate error correction circuits for each data group.
Solution Approach 2:
The check matrix parameters are specifically designed with Hamming distances of 1 or M/2 between group indicators, and the syndrome calculation uses modular arithmetic properties. These parameter optimizations enable the error correction circuit to efficiently distinguish between errors in different data groups while maintaining a compact circuit structure.
3Measurement precision
If Hamming distance between group indicators is set to 1 or M/2, then error correction accuracy is improved, but calculation overhead increases
Solution Approach 1:
The check matrix is pre-configured with group indicators that have Hamming distances of 1 or M/2 between neighboring data groups. This preliminary structuring of the check matrix enables the error correction circuit to quickly identify error locations and types without requiring complex real-time calculations, thus improving accuracy while minimizing calculation time.
Data Source
AI summary
A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.