Two-Level ECC Check-Bit Sharing for Low-Latency Memory Arrays
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Solution Overview
Problem
Existing memory systems face challenges in protecting data integrity due to bit corruption caused by environmental and internal factors, requiring efficient error correction mechanisms that balance error detection and correction capabilities with overhead and latency considerations.
Innovation Solution
A two-level error correction code (ECC) system is implemented, comprising a first level ECC for error detection in smaller words and a second level ECC for error correction in larger words, with shared check bits to minimize overhead and latency, using a memory controller that includes first and second level ECC circuits to manage data integrity across memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-level ECC system is used for error correction in large words, then error correction capability is provided, but overhead and latency increase
Solution Approach 1:
The ECC system is divided into two levels: first level ECC circuits operate on smaller words (e.g., 64 bits) for fast error correction, while second level ECC circuits operate on larger words (e.g., 512 bits) for comprehensive error correction. This segmentation allows the system to handle small errors quickly at the first level, reducing overall latency while maintaining strong error correction capability for larger errors at the second level.
Solution Approach 2:
The first level ECC provides partial error correction for smaller words, handling the majority of error cases that occur in practice. This partial action at the first level reduces the burden on the second level, allowing the system to achieve full error correction capability without requiring the second level to process every error, thereby reducing latency.
2Reliability
If a single-level ECC system is used for error correction in large words, then error correction capability is provided, but overhead increases
Solution Approach 1:
The ECC functionality is segmented into two levels with different correction capabilities. The first level handles common single-bit errors with minimal overhead, while the second level provides additional correction capability for multi-bit errors. This segmentation reduces total overhead compared to implementing a single-level ECC system with full correction capability for all error types.
Solution Approach 2:
The two-level ECC system provides multi-functionality: the first level ECC circuits handle fast correction for small words, while the second level ECC circuits provide comprehensive correction for large words. This universal approach allows the same memory system to efficiently handle both small and large word errors, reducing the need for separate specialized systems.
3Reliability
If two-level ECC is implemented without sharing check bits, then error detection and correction are provided, but overhead and latency increase
Solution Approach 1:
The first and second level ECC systems are merged through shared check bits. The check bits generated by the first level ECC for smaller words are also utilized by the second level ECC for larger words. This merging eliminates redundant check bit generation and storage, reducing overhead and access latency while maintaining comprehensive error detection and correction capabilities.
4Reliability
If two-level ECC is implemented without sharing check bits, then error detection and correction are provided, but overhead increases
Solution Approach 1:
The first and second level ECC systems share check bits, merging their functionality. The check bits generated at the first level for smaller data blocks are reused by the second level for larger blocks, eliminating redundant check bit storage and reducing memory overhead. This merging reduces the total number of check bits required while maintaining comprehensive error detection and correction.
Data Source
AI summary
A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.