Memory ECC Re-Correction Using Chip-Kill Miscorrection Detection
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Solution Overview
Problem
As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, leading to the need for error correction methods like redundancy cells and error correction circuits, but these methods may not always ensure efficient error correction.
Innovation Solution
An improved error correction method and memory system that includes reading data and error correction codes from multiple memory chips, identifying and designating a 'chip-killed' memory chip when miscorrections occur, and repeatedly re-correcting errors by swapping the chip-killed memory chip until no miscorrection is detected, using error correction codes like Reed Solomon, Bose-Chaudhuri-Hocquenghem, or Turbo schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to correct errors in memory systems, then error correction capability is improved, but the number of bits required for error correction codes increases
Solution Approach 1:
The patent segments the error correction process into multiple stages: initial error correction using ECC codes, miscorrection detection through syndrome checking, and iterative chip identification. By dividing the correction process, the system achieves reliable error correction while using fewer total bits compared to traditional single-stage correction methods that would require larger ECC codes to handle all error cases.
Solution Approach 2:
The patent implements a dynamic error correction approach where the system adaptively identifies and isolates defective memory chips through iterative syndrome checking and chip killing. This dynamic process allows the system to correct errors efficiently by focusing computational resources only on identified problematic areas rather than applying comprehensive correction to all memory cells, reducing the overall bits required.
2Measurement precision
If iterative re-correcting process is implemented to handle miscorrections, then error correction accuracy is improved, but detection time and operational complexity increase
Solution Approach 1:
The patent performs preliminary error correction using ECC codes before initiating the iterative miscorrection detection process. By pre-correcting obvious errors and only then proceeding to detect miscorrections through syndrome checking, the system reduces the overall detection time compared to methods that would perform exhaustive checking from the beginning.
Solution Approach 2:
The patent extracts and isolates the miscorrection detection as a separate function from the main error correction process. By using syndrome checking to identify miscorrections and then selectively re-correcting only affected data portions, the system achieves high accuracy without requiring full-system re-checking, thereby reducing detection time.
3Measurement precision
If iterative re-correcting process is implemented to handle miscorrections, then error correction accuracy is improved, but operational complexity increases
Solution Approach 1:
The patent implements a universal syndrome checking mechanism that serves multiple functions: initial error detection, miscorrection identification, and verification of correction accuracy. This multi-functional approach reduces operational complexity compared to systems that would require separate dedicated circuits for each error handling stage.
Solution Approach 2:
The patent uses feedback from syndrome checking results to control the iterative correction process. The syndrome information feeds back to determine whether further re-correcting is needed and which specific chips should be targeted, creating a self-regulating system that reduces operational complexity by automatically adjusting the correction process based on detected error patterns.
Data Source
AI summary
An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory chips as a chip-killed memory chip when a miscorrection occurs; re-correcting the error of the data based on the error correction code in consideration of the designated chip-killed memory chip; and re-determining whether a miscorrection occurs in the re-correcting of the error of the data.