Memory ECC Circuit for Chip-Kill and Random Multi-Bit Errors
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Solution Overview
Problem
As memory devices become more highly integrated, the probability of multi-bit errors increases, making it difficult for existing error correction circuits to efficiently handle both chip-kill and random errors, leading to increased ECC decoding latency and system performance degradation.
Innovation Solution
A memory system with an error correction circuit that includes an address storage circuit and a failed chip detection circuit, which detects and corrects error bits, stores addresses of data with excessive error bits, and identifies failed memory chips by writing test data and reading it back, allowing for reduced parity bits and increased random error coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of memory device is increased, then storage capability is improved, but the probability of defective memory cells and multi-bit errors increases
Solution Approach 1:
The error correction approach is segmented into two distinct modes: a first error correction mode for chip-kill errors and a second error correction mode for random multi-bit errors. This segmentation allows the system to apply different correction strategies based on the error type, improving overall reliability while maintaining high storage capacity
Solution Approach 2:
The system dynamically changes operational parameters by switching between different error correction modes based on the detected error pattern. When a chip-kill error is detected, the first mode with reduced parity bits is applied; when random errors are detected, the second mode with enhanced correction capability is applied, optimizing the balance between storage capacity and reliability
2Reliability
If traditional error correction circuits are used to handle both chip-kill and random errors, then comprehensive error coverage is achieved, but ECC decoding latency increases
Solution Approach 1:
The error correction circuit operates dynamically by switching between two different correction modes based on the error type detected. The system adapts its correction strategy in real-time: using the first mode for chip-kill errors and the second mode for random errors, thereby minimizing decoding latency while maintaining comprehensive error coverage
Solution Approach 2:
Different error correction qualities are applied to different error types. The first error correction mode provides optimized correction for chip-kill errors with lower latency, while the second mode provides enhanced correction for random multi-bit errors. This local optimization of correction quality based on error type reduces overall decoding latency
3Reliability
If more parity bits are used to correct random multi-bit errors, then error correction capability is improved, but the number of parity bits increases
Solution Approach 1:
The parity bit allocation is segmented into two different configurations: a first parity configuration for chip-kill error correction and a second parity configuration for random multi-bit error correction. This segmentation allows the system to use more parity bits only when needed for random errors, rather than always using the maximum number of parity bits
Solution Approach 2:
The system applies partial error correction action by using different parity bit configurations based on the error type. For chip-kill errors, a reduced parity configuration is used, while for random errors, an excessive parity configuration provides enhanced correction capability. This partial application of full correction resources optimizes the balance between reliability and resource usage
Data Source
AI summary
A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.