Memory Module ECC Remapping for Chip-Kill Overhead Reduction
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Solution Overview
Problem
Existing memory systems face challenges in reducing Error Correction Code (ECC) overhead while maintaining robust error detection and correction capabilities, particularly during chip-kill operations involving memory device failures.
Innovation Solution
A memory module design that assigns data chips to sub-channels, uses a shared ECC chip for error correction, and employs a registered clock driver controller to manage pin mappings, allowing for reduced ECC chip usage and efficient chip-kill operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC overhead is used to maintain robust error detection and correction capabilities, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies universality by enabling ECC chips to serve dual purposes: their primary function of error correction and a secondary function as spare memory chips for chip-kill operations. When a data chip fails, the ECC chip can be dynamically reconfigured to replace the failed data chip, allowing one component to fulfill multiple roles and reducing the need for dedicated spare chips.
Solution Approach 2:
The patent employs parameter changes by dynamically reconfiguring the mapping between I/O pins and memory chips. The controller can change the functional assignment of ECC chips from error correction to data storage based on failure conditions, and can remap I/O pins to connect different chips to different pin groups, enabling flexible adaptation without hardware changes.
2Reliability
If additional memory channels and memory devices are required for chip-kill operations, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies universality by enabling ECC chips to serve dual purposes: their primary function of error correction and a secondary function as spare memory chips for chip-kill operations. When a data chip fails, the ECC chip can be dynamically reconfigured to replace the failed data chip, allowing one component to fulfill multiple roles and reducing the need for dedicated spare chips.
Solution Approach 2:
The patent employs parameter changes by dynamically reconfiguring the mapping between I/O pins and memory chips. The controller can change the functional assignment of ECC chips from error correction to data storage based on failure conditions, and can remap I/O pins to connect different chips to different pin groups, enabling flexible adaptation without hardware changes.
3Reliability
If more memory chips are used to maintain RAS features, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies universality by enabling ECC chips to serve dual purposes: their primary function of error correction and a secondary function as spare memory chips for chip-kill operations. When a data chip fails, the ECC chip can be dynamically reconfigured to replace the failed data chip, allowing one component to fulfill multiple roles and reducing the need for dedicated spare chips.
Solution Approach 2:
The patent employs parameter changes by dynamically reconfiguring the mapping between I/O pins and memory chips. The controller can change the functional assignment of ECC chips from error correction to data storage based on failure conditions, and can remap I/O pins to connect different chips to different pin groups, enabling flexible adaptation without hardware changes.
Data Source
AI summary
A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.