Memory Controller ECC Scaling for Compressed Far Memory
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Solution Overview
Problem
Existing computing systems face bottlenecks in system memory performance, particularly due to higher error rates in emerging non-volatile memory technologies used in far memory, which can lead to data integrity issues, especially in enterprise environments with large amounts of redundant data.
Innovation Solution
Implementing a multi-level system memory architecture with near memory as a faster cache and far memory as a non-volatile memory technology, where data is compressed to utilize extra space for error correction code (ECC) expansion, and using adjustable ECC generation based on compression levels to enhance error protection, especially in regions prone to higher bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in far memory using emerging non-volatile memory technology, then storage capacity and non-volatility are improved, but bit error rate increases
Solution Approach 1:
The patent dynamically adjusts the ECC code size parameter based on the type of far memory being used. When non-volatile far memory with higher bit error rates is detected, the system increases the ECC code size to provide enhanced error correction capability. This parameter adaptation resolves the contradiction by matching the error protection level to the actual error characteristics of the storage medium.
Solution Approach 2:
The system implements dynamic ECC generation that adapts to different memory configurations and error conditions. The ECC code size is not fixed but is determined at runtime based on the far memory type, allowing the error protection mechanism to dynamically respond to the actual bit error rate conditions of the deployed hardware.
2Reliability
If ECC code size is increased to protect against higher bit error rates, then data integrity is improved, but storage capacity is reduced
Solution Approach 1:
The patent changes the ECC code size parameter based on the far memory type. For volatile far memory with lower error rates, a smaller ECC code size is used, preserving more storage capacity. For non-volatile far memory with higher error rates, a larger ECC code size is applied to ensure data integrity. This selective parameter adjustment resolves the contradiction by matching error protection overhead to the actual error characteristics of the memory medium.
Solution Approach 2:
The system applies different levels of error protection (different ECC code sizes) to different types of far memory based on their specific error characteristics. This localized quality approach ensures that high error protection is applied only where needed (non-volatile memory), while volatile memory uses lighter protection, thus optimizing the balance between reliability and storage capacity.
3Speed
If system memory speed is increased, then processing performance is improved, but power consumption increases
Solution Approach 1:
The patent segments the memory system into near memory (fast, volatile) and far memory (slower, non-volatile). Frequently accessed data is kept in the fast near memory for quick processing, while less frequently accessed data is stored in the energy-efficient non-volatile far memory. This segmentation allows the system to achieve fast processing when needed while consuming less power overall by utilizing the energy-efficient far memory for bulk storage.
Solution Approach 2:
The system uses a cache coherence protocol that periodically synchronizes data between near memory and far memory. This periodic action allows the fast near memory to operate independently for short periods, providing high-speed access when needed, while the system as a whole benefits from the lower power consumption of non-volatile far memory for persistent storage.
Data Source
AI summary
An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression circuitry to compress a cache line data structure to be written into a system memory. The memory controller logic circuitry has adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry. The memory controller logic having circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.