Integrated Memory Assembly ECC via Control Die Decoding
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Solution Overview
Problem
Current non-volatile semiconductor memory devices face challenges in efficiently managing data storage and retrieval due to limitations in decoding codewords, particularly in high bit error rates and power consumption, especially when decoding on the memory controller rather than the control die.
Innovation Solution
An integrated memory assembly with a control die and memory die, where the control die encodes and decodes codewords, including data and parity bits, and communicates efficiently with a memory controller, using different decoding techniques to manage bandwidth and power consumption, and estimates bit error rates to optimize decoding decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoding is performed on the memory controller, then error correction capability is improved, but power consumption and bandwidth usage increase
Solution Approach 1:
The patent divides the decoding function into two segments: a first decoder on the control die that performs initial error correction, and a second decoder on the memory controller that handles remaining errors. This segmentation allows the system to achieve high error correction capability while reducing power consumption by handling most corrections at the lower-power control die location.
Solution Approach 2:
The control die acts as an intermediary between the memory die and the memory controller. It performs preliminary decoding and error correction, then selectively transfers only uncoded or partially corrected data to the memory controller, reducing the burden on the controller and overall power consumption.
2Reliability
If decoding is performed on the memory controller, then error correction capability is improved, but bandwidth consumption increases
Solution Approach 1:
The patent segments the decoding process so that the control die handles initial error correction locally, reducing the amount of data that needs to be transferred to the memory controller for further processing. This segmentation decreases bandwidth consumption while maintaining error correction capability.
Solution Approach 2:
The control die serves as an intermediary that performs preliminary decoding operations, filtering out many errors before data reaches the memory controller. This reduces the quantity of data requiring high-bandwidth transmission between controller and memory.
3Use of energy by moving object
If decoding is performed on the control die, then power consumption is reduced, but error correction capability may be limited
Solution Approach 1:
The patent implements a two-stage decoding architecture where the control die performs initial error correction (consuming less power) and the memory controller provides additional error correction capability for difficult cases. This segmentation balances power consumption and error correction capability.
Solution Approach 2:
The control die acts as an intermediary that performs preliminary decoding with lower power consumption, then selectively refers difficult cases to the memory controller for enhanced error correction, achieving both power efficiency and high reliability.
4Reliability
If data is transferred from control die to controller for decoding, then error correction capability is improved, but bandwidth is wasted
Solution Approach 1:
The patent segments the error correction function between control die and memory controller, allowing the control die to handle routine corrections locally and transfer only necessary data to the controller, minimizing bandwidth usage while maintaining error correction capability.
Solution Approach 2:
The control die serves as an intermediary that performs local error correction, filtering out many errors before data transfer to the memory controller. This reduces the amount of bandwidth-consuming data transmission while preserving error correction capability.
Data Source
AI summary
Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.