Semiconductor Memory ECC and DBI Circuits for Faster Error Correction
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently addressing sporadic defective bits post-packaging and high processing times for error correcting functions, which affect performance and power consumption.
Innovation Solution
Implementing error correction coding (ECC) and data bus inversion (DBI) operations within semiconductor devices, including ECC control circuits that perform ECC encoding and decoding in parallel, reducing the need for redundant circuits and optimizing data transfer by using a common determinant (H-Matrix) for ECC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction coding (ECC) operations are performed using traditional sequential methods, then data accuracy is improved, but processing time increases and device performance deteriorates
Solution Approach 1:
The patent segments the ECC processing into multiple parallel operations by dividing the data bus into multiple channels. Each channel performs ECC encoding independently and simultaneously, allowing the system to process larger data volumes without increasing per-operation processing time. This segmentation enables parallel execution of ECC tasks that would traditionally be sequential.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple ECC encoding paths operating simultaneously. Instead of processing data through a single ECC pipeline sequentially, the system creates multiple independent encoding dimensions that operate in parallel, effectively transforming the time dimension into a spatial dimension with multiple processing channels.
2Reliability
If redundant word lines or bit lines are used to replace defective bits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error correction functionality from the physical circuit structure (redundant word lines and bit lines) and implements it through logical ECC operations. Instead of adding redundant physical circuits to replace defective bits, the system uses ECC algorithms to detect and correct errors in the data stream, separating the correction function from the storage structure.
Solution Approach 2:
The patent replaces the mechanical/physical approach of redundant circuit wiring with an algorithmic/software-based ECC system. Rather than physically routing additional word lines and bit lines to replace defective ones, the system uses mathematical error correction codes to identify and correct defective bit patterns in the data, substituting computational methods for physical circuit solutions.
3Loss of energy
If data bus inversion (DBI) encoding is applied to reduce signal transitions, then power consumption is reduced, but processing overhead increases
Solution Approach 1:
The patent merges the DBI encoding operation with the ECC encoding operation into a unified processing pipeline. Instead of performing DBI encoding separately after ECC encoding (which would double the processing overhead), the system combines both functions into a single integrated operation that achieves both error correction and transition reduction without proportional increases in processing time.
Data Source
AI summary
Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.