Semiconductor Memory ECC and DBI Parallel Processing
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently addressing sporadic defective bits and high power consumption due to the time-consuming nature of error correcting functions, particularly with the use of ECC encoding and decoding processes.
Innovation Solution
The implementation of error correction coding (ECC) and data bus inversion (DBI) operations within semiconductor devices, including the use of ECC control circuits that perform ECC encoding and decoding in parallel, reducing the need for additional error correction coding and optimizing data processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC encoding and decoding operations are performed sequentially, then error correction functionality is achieved, but processing time increases and device performance deteriorates
Solution Approach 1:
The patent divides the error correction process into two independent segments: ECC encoding operations and ECC decoding operations. These segments are processed in parallel through separate processing paths within the semiconductor device, allowing simultaneous execution without interference. This segmentation enables the device to maintain full error correction capability while halving the effective processing time compared to sequential operations.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing architecture. By introducing multiple processing dimensions (separate encoding and decoding paths), the system can handle multiple error correction operations simultaneously, effectively adding a temporal dimension to the processing capability and dramatically reducing overall processing time.
2Reliability
If multiple ECC encoding and decoding operations are performed sequentially, then comprehensive error correction is achieved, but processing time increases
Solution Approach 1:
The patent segments the error correction workload into distinct encoding and decoding operations that can be independently processed. Multiple such segmented operations can then be distributed across parallel processing paths, allowing comprehensive error correction coverage to be achieved without proportionally increasing processing time, thereby maintaining high data processing efficiency.
Solution Approach 2:
The patent merges multiple ECC processing operations into a unified parallel processing framework. By combining encoding and decoding operations into the same parallel architecture, the system achieves comprehensive error correction while utilizing shared resources efficiently, preventing the processing time from scaling linearly with the number of operations.
3Loss of energy
If Data Bus Inversion (DBI) encoding is applied to reduce signal transitions, then power consumption decreases, but additional processing steps are required
Solution Approach 1:
The patent merges DBI encoding operations with the parallel ECC processing architecture. By integrating DBI functionality into the existing parallel processing framework, the system can apply power-saving inversion encoding without adding significant processing complexity. The merged architecture handles both ECC and DBI operations through unified parallel paths, minimizing the increase in device complexity while achieving reduced power consumption.
Solution Approach 2:
The patent creates a universal processing architecture that handles multiple functions: ECC encoding, ECC decoding, and DBI encoding. This multi-functional design allows the same parallel processing resources to serve multiple purposes, reducing the need for separate dedicated circuits for each function and thereby limiting the increase in processing complexity despite the added DBI capability.
Data Source
AI summary
Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.