Memory ECC-DBI-DM Parallel Processing for Lower Write Latency
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Solution Overview
Problem
Current memory systems face challenges in optimizing area, power consumption, and operating time due to the limitations of existing ECC, DBI, and DM unit operations, particularly in parallel operation and power efficiency.
Innovation Solution
A memory system that includes an ECC unit for error correction, a DBI unit for data inversion, and a DM unit that operates independently to minimize high logic bits, reducing power consumption and latency by optimizing data masking and inversion operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC unit and DM unit are integrated and operate sequentially, then reliability is improved through error correction, but operating time increases due to sequential processing
Solution Approach 1:
The patent divides the error correction and data masking functions into separate ECC unit and DM unit that operate independently and in parallel, rather than sequentially. This segmentation allows both units to process data simultaneously, reducing total operating time while maintaining the reliability benefits of both error correction and data masking functions.
Solution Approach 2:
The DM unit generates DM flags based on second data before the ECC unit completes its correction process. This preliminary action allows the data masking decisions to be made in advance, enabling parallel operation and reducing the overall processing time while still ensuring data reliability through subsequent ECC correction.
2Measurement precision
If DM unit operates based on corrected third data, then data accuracy is improved, but operating time increases due to waiting for ECC completion
Solution Approach 1:
The DM unit performs its operation in advance using the second data received from the channel, before the ECC unit completes the correction process. This preliminary action generates DM flags that will be applied to the corrected data later, eliminating the need for the DM unit to wait for ECC completion and thus reducing latency while maintaining data accuracy.
Solution Approach 2:
The system dynamically adjusts the operation timing of different units. The DM unit operates on second data while the ECC unit processes the same second data to produce third data. The DM flags generated from second data are then applied to third data, creating a flexible timing arrangement that enables parallel processing and reduces latency.
3Adaptability or versatility
If all units (ECC, DBI, DM) are fully integrated, then functionality is improved, but area consumption increases
Solution Approach 1:
The patent segments the functionality into separate units (ECC unit, DBI unit, DM unit) that can be independently configured and activated. This allows the system to include only the necessary units based on specific application requirements, reducing area consumption while maintaining the ability to provide full functionality when needed. Each unit is independently optimizable for area efficiency.
Solution Approach 2:
The DM unit is designed to operate independently of the ECC unit, and both units can process the same data input. This multi-functionality allows the system to achieve comprehensive data protection and processing capabilities through separate, optimized units rather than a single large integrated block, improving area efficiency while maintaining versatility.
4Loss of energy
If DM unit processes data after ECC correction, then power consumption is reduced by processing smaller data sets, but operating time increases due to sequential operation
Solution Approach 1:
The patent segments the data processing into parallel streams where the DM unit processes second data independently while the ECC unit processes the same second data separately. This segmentation enables both units to operate simultaneously on the full data set, maintaining power efficiency by having the DM unit work on manageable data portions while eliminating sequential processing delays.
Data Source
AI summary
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.