Memory System ECC Decoding Optimization

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Solution Overview

Problem

In memory systems, the execution of error correction decoding operations is often unnecessary due to low error probabilities during data transmission, leading to degraded write operation speeds and increased processing times.

Innovation Solution

Implementing a memory system with a host ECC encoder and a module controller that performs ECC encoding and decoding operations, where the ECC decoding operation is only executed when errors are detected, allowing for a first write operation without error correction and a second write operation with error correction, thereby optimizing write speed by reducing unnecessary decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC decoding operation is always executed during write operations, then data reliability is improved, but write operation speed deteriorates due to unnecessary decoding processes

Engineering Contradiction:
Improvedata reliabilityVSAvoidwrite operation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements partial action by conditionally executing ECC decoding only when errors are detected during data transmission. The module controller checks for errors in the received write data and performs ECC decoding selectively rather than unconditionally, thus avoiding unnecessary decoding operations while maintaining data reliability when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent applies dynamics by making the ECC decoding operation dynamic and adaptive based on actual error conditions. The system transitions from a static always-on decoding approach to a dynamic conditional approach where decoding is activated only when error detection mechanisms identify corrupted data, optimizing performance based on real-time conditions.

Inventive Principle:
Principle #15Dynamics

2Productivity

If ECC decoding operation is skipped to improve write speed, then write operation speed is improved, but data reliability deteriorates when errors occur

Engineering Contradiction:
Improvewrite operation speedVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms where the module controller continuously monitors data transmission for errors and uses this feedback information to determine whether ECC decoding should be executed. The error detection results feed back into the control logic, creating a closed-loop system that adapts the decoding operation based on actual transmission conditions, thus maintaining reliability while optimizing speed.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-service by automatically detecting errors and triggering ECC decoding only when necessary, without requiring external intervention or continuous monitoring. The module controller autonomously manages the decoding operation based on its own error detection capabilities, making the system both efficient and reliable.

Inventive Principle:
Principle #25Self-service

3Reliability

If parity data is always removed and ECC decoding is always performed, then error correction capability is maintained, but processing time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing parity removal and ECC decoding only partially - specifically, only when error detection indicates that decoding is necessary. This selective approach reduces the average processing time across all write operations while maintaining full error correction capability when errors are actually present in the transmitted data.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11106533B2Memory systems and writing methods of the memory systems
Publication Date: 2021.08.31 SK HYNIX INC
  • US11106533B2 patent drawing
  • US11106533B2 patent drawing
  • US11106533B2 patent drawing

AI summary

A memory system includes a host error correction code (ECC) encoder and a memory module. The host ECC encoder performs a host ECC encoding operation of write data to output host ECC encoded data, and the memory module includes a memory medium receiving the host ECC encoded data and a module controller controlling the memory medium. The module controller includes a parity remover and a module ECC decoder. The parity remover removes parity data from the host ECC encoded data to generate parity-removed data and performs a first write operation for writing the parity-removed data into the memory medium. The module ECC decoder performs a module ECC decoding operation of the host ECC encoded data to generate module ECC decoded data and performs a second write operation for writing the module ECC decoded data into the memory medium.