Memory Module ECC Layering for Die Failure and Random Error Protection

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Solution Overview

Problem

Existing memory technologies, such as DDR5 and DDR6, struggle with efficient error correction when additional metadata is stored, leading to weakened detection and correction capabilities due to reduced parity bits, and fail to provide adequate protection against simultaneous die failures and random errors.

Innovation Solution

Implementing a combination of on-die ECC bits with host ECC using XOR and BCH/CRC codes for enhanced error protection, incorporating multilayer coding to safeguard data and metadata, and employing cyclic redundancy checks to correct single bit random errors and die failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If additional metadata is stored on die, then storage capacity is improved, but the number of available parity bits is reduced, weakening the detection and correction capability of ECC

Engineering Contradiction:

Improvestorage capacityVSAvoiddetection and correction capability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the error correction system into two independent layers: on-die SEC (Single Error Correction) and host-level RS (Reed-Solomon) ECC. The on-die SEC handles single-bit errors using minimal parity bits, while the host-level RS ECC handles multiple-bit errors and metadata protection. This segmentation allows metadata to be stored without compromising the multi-bit error correction capability, as each layer operates independently with its own error correction mechanism.

Inventive Principle:

Principle #1Segmentation

2Reliability

If on-die SEC is used to correct single errors, then single error correction is improved, but the system fails to provide adequate protection against simultaneous die failures and multiple errors

Engineering Contradiction:

Improvesingle error correctionVSAvoidprotection against multiple error types

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent adds a new dimension to error correction by implementing host-level RS (Reed-Solomon) ECC that operates independently from on-die SEC. This additional layer provides protection against multiple-bit errors, simultaneous die failures, and metadata corruption, while on-die SEC continues to handle single-bit errors. The multi-layer approach enables the system to address diverse error types without compromising single-error correction performance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12487882B2System and method for protecting data using cyclic properties of error correcting code

Publication Date: 2025.12.02 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.