Configurable Memory ECC Modes for Double-Error Detection
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Solution Overview
Problem
Memory devices, particularly DRAM, face challenges in maintaining data integrity due to internal errors, with existing error correction mechanisms either failing to correct double-bit errors accurately or inadvertently introducing additional errors, which is critical in applications requiring high reliability such as automotive systems.
Innovation Solution
The memory device is designed to be configurable between Single Error Correction (SEC) and Single Error Correction Double Error Detection (SECDED) modes, allowing it to selectively implement error correction operations without increasing die size, by repurposing SEC circuitry for SECDED and adjusting error detection codeword granularity, ensuring accurate error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error correction mechanisms are implemented, then single-bit errors can be corrected, but double-bit errors cannot be corrected accurately and additional errors may be introduced
Solution Approach 1:
The patent implements dynamic error correction mode selection, allowing the memory device to switch between SEC and SECDED modes based on operational requirements. The error correction circuitry is designed to be reconfigurable, enabling it to adapt its correction capability (single-bit vs. double-bit error detection and correction) without requiring separate dedicated circuits for each mode, thus resolving the contradiction between correction accuracy and error introduction risk.
Solution Approach 2:
The patent changes the operational parameters of the error correction circuitry by adjusting the granularity of error detection codewords and selecting different correction modes (SEC or SECDED) based on the specific error scenario. This parameter adjustment allows the system to optimize error correction performance for different error types, preventing additional errors from being introduced while maintaining high correction accuracy.
2Reliability
If SECDED mode is implemented to detect double-bit errors, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent designs the error correction circuitry to be multi-functional, capable of operating in both SEC and SECDED modes using the same hardware resources. The error detection codeword granularity is adjusted dynamically to enable SECDED functionality without requiring separate dedicated circuits, thus improving double-error detection capability while minimizing the increase in device complexity.
Solution Approach 2:
The error correction system is designed with dynamic reconfigurability, allowing it to switch between different operational modes (SEC and SECDED) based on the required error detection capability. This dynamic approach enables the circuitry to perform multiple functions with a single unified design, reducing overall device complexity while maintaining the ability to detect double-bit errors when needed.
3Reliability
If error correction operations are implemented, then data integrity is maintained, but die size increases
Solution Approach 1:
The patent segments the error correction functionality into modular components that can be selectively activated. By dividing the error correction circuitry into separate error detection and correction modules with configurable granularity, the design maintains data integrity through comprehensive error correction while minimizing the overall die size by only implementing the necessary correction capabilities for each specific application scenario.
Solution Approach 2:
The patent optimizes the granularity of error detection codewords to balance data integrity protection with die size constraints. By adjusting the codeword granularity parameter, the system achieves effective error correction for the required data sizes without unnecessarily increasing the die area, thus maintaining data integrity while controlling the physical footprint of the error correction circuitry.
Data Source
AI summary
Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.