Memory ECC Layout for Sub-Word Line Driver Defect Detection

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Solution Overview

Problem

As semiconductor memory devices increase in capacity, it becomes challenging to fabricate memory devices without defective memory cells, leading to the need for error correction methods such as ECC circuits to correct errors in memory systems.

Innovation Solution

The implementation of a memory system that includes an error correction code generation circuit, a memory core with N+1 cell regions for storing data groups and error correction codes, and an error correction circuit to correct errors based on the error correction codes generated using a specific check matrix.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases

Engineering Contradiction:
Improvememory capacityVSAvoiddefect-free memory cells
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory data is divided into multiple data groups (N groups of K-bit data each), and error correction codes are generated for each group separately using the check matrix. This segmentation allows targeted error correction for each data group, improving overall reliability while maintaining high capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Error correction codes serve as an intermediary mechanism between the data groups and the error correction process. The check matrix acts as a mathematical intermediary that transforms the N data groups into M-bit error correction codes, enabling systematic error detection and correction across the entire memory system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If error correction codes are generated for each data group, then error correction capability is improved, but computational complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror correction computation
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The check matrix uses specific parameter configurations where the Hamming distance between group indicators for neighboring data groups is set to 1 or M/2. This parameter optimization reduces the computational complexity of error correction while maintaining robust error correction capability across all data groups.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The error correction system generates codes for all N data groups using the full check matrix, providing comprehensive error protection. The Hamming distance requirement ensures that even partial error patterns (such as errors in neighboring groups) are effectively detected and corrected, making the system robust without requiring excessive computational resources.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12288594B2Memory and operation method of memory
Publication Date: 2025.04.29 SK HYNIX INC
  • US12288594B2 patent drawing
  • US12288594B2 patent drawing
  • US12288594B2 patent drawing

AI summary

A memory includes a first check matrix calculation circuit configured to generate a first parity based on a group indicator portion of a check matrix and write data; a memory core including cell regions configured to store therein the write data and the first parity, neighboring ones of the cell regions sharing one or more sub-word line drivers; a first syndrome calculation circuit configured to generate a first syndrome based on the first parity read from the memory core and a first result of calculating the group indicator portion and data read from the memory core; and a failure determination circuit configured to detect, for each row of the memory core, a defective one of the sub-word line drivers based on the first syndrome.