Memory ECC Decoding with Error-Level-Based Engine Switching
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Solution Overview
Problem
Existing decoding circuits in memory devices face a challenge in balancing power consumption and decoding success rate, as higher complexity algorithms for better success rates also increase power consumption, and simpler algorithms may not effectively correct errors.
Innovation Solution
A decoding method that configures multiple message channels in an error checking and correcting circuit to determine error level information, routing the codeword to either a low-power, low-success-rate decoding engine or a high-power, high-success-rate engine based on error levels, optimizing power consumption while maintaining decoding accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decoding algorithm with higher complexity is adopted to improve decoding success rate, then the decoding success rate is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic selection between two decoding engines (first and second decoding engines) based on the error level of the input codeword. The error checking and correcting circuit dynamically determines which decoding engine to use, switching between low-power and high-performance modes according to the actual error conditions, thereby resolving the contradiction between power consumption and decoding success rate.
Solution Approach 2:
The patent changes the operational parameters of the decoding circuit by selecting different decoding engines with different complexity levels based on the error level parameter. When the error level is low, a simpler decoding algorithm is used; when the error level is high, a more complex decoding algorithm is activated, thus adapting the power consumption and performance parameters to the actual needs.
2Use of energy by moving object
If a simpler decoding algorithm is used to reduce power consumption, then the power consumption is reduced, but the decoding success rate decreases
Solution Approach 1:
The system dynamically adjusts the decoding complexity based on the error level of the input data. The error checking and correcting circuit evaluates the error level and dynamically selects the appropriate decoding engine, ensuring that the decoding success rate is maintained when needed while reducing power consumption when errors are minimal.
Solution Approach 2:
The patent changes the decoding algorithm complexity parameter based on the error level condition. By adjusting this parameter dynamically, the system achieves low power consumption for simple cases while maintaining high decoding success rate for complex cases with higher error levels.
Data Source
AI summary
A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.


