Memory ECC Decoding With Erasure Information for 2-Bit Correction
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Solution Overview
Problem
High integration or miniaturization of memory devices increases the likelihood of errors during data read and write operations, necessitating improved error correction capabilities with limited system resources.
Innovation Solution
A memory device stores erasure information and uses it for single-bit error correction and double-bit error detection (SEC-DED) to correct 2-bit errors, employing a syndrome calculator, bit calculator, decoder, and data converter to determine and correct errors based on erasure information and H-matrix components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration or miniaturization is applied to memory devices, then storage capacity increases, but error occurrence probability increases
Solution Approach 1:
The patent stores erasure information (position information of codewords containing erasures) in advance in the memory region before actual data operations. When an error occurs, this pre-stored information enables faster and more accurate error correction by immediately identifying which codewords may contain errors, rather than detecting errors after they occur during normal read/write operations.
2Reliability
If traditional error correction methods are used, then error correction capability is provided, but system resources are excessively consumed
Solution Approach 1:
Instead of applying uniform error correction across all memory operations, the patent selectively applies enhanced error correction only to specific codewords identified through erasure information. The system distinguishes between codewords that may contain errors (those with stored erasure information) and normal codewords, applying different correction strategies accordingly. This localized approach reduces overall system resource consumption while maintaining robust error correction where needed.
Solution Approach 2:
The patent modifies the traditional SEC-DED error correction parameters by incorporating erasure information to achieve 2-bit error correction capability. By changing the correction parameters from single-bit to double-bit correction for identified error-prone codewords, the system improves reliability without proportionally increasing resource usage, as the enhanced correction is applied selectively rather than universally.
3Reliability
If 2-bit error correction is implemented, then error correction efficacy improves, but implementation cost increases
Solution Approach 1:
The patent implements 2-bit error correction capability selectively rather than universally. By using erasure information to identify only those codewords that require enhanced correction, the system applies the more complex (and costly) 2-bit correction algorithm only when necessary, while using standard correction methods for other codewords. This partial application approach achieves improved error correction efficacy where needed while controlling overall implementation costs.
Data Source
AI summary
An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.