Memory ECC Erasure Decoding for Localized Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in extending the lifespan of physical memory due to the limitations of conventional error correction codes (ECCs), which often lead to unnecessary replacement of memory modules and reduced error correction capabilities when errors are concentrated in specific regions or distributed across multiple memory devices.
Innovation Solution
The implementation of selective erasure decoding, which utilizes erasure information to declare erasure locations within memory devices, allowing for targeted error correction across different memory hierarchy levels and reducing the likelihood of non-recoverable errors by applying erasure decoding to specific locations rather than declaring entire devices faulty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is used for error correction, then errors can be detected and corrected, but the total number of correctable errors is limited and entire devices must be declared faulty when errors occur
Solution Approach 1:
The patent segments the memory system into multiple memory devices and further into specific locations within each device. Instead of treating entire devices uniformly, the system identifies and marks specific locations (rows, columns, or blocks) where erasure errors have occurred. This segmentation allows selective application of erasure decoding only to affected locations rather than declaring entire devices faulty, thereby increasing the number of correctable errors while maintaining system reliability.
Solution Approach 2:
The patent implements dynamic error handling by maintaining erasure information that is updated based on detected errors. The system adaptively adjusts which locations receive erasure decoding treatment based on the specific error patterns observed. This dynamic approach allows the system to flexibly respond to different error scenarios, maximizing the use of available ECC resources and extending memory lifespan without requiring static device-level fault declarations.
2Reliability
If storage redundancy or spare memory resources are configured to handle errors, then memory reliability is improved, but system cost increases
Solution Approach 1:
The patent enables the memory system to self-diagnose and self-correct errors by implementing erasure decoding using existing ECC resources. The system automatically detects error locations, maintains erasure information, and applies corrective decoding without requiring external redundancy mechanisms or spare memory modules. This self-service capability allows the system to handle errors using only the originally allocated memory resources, avoiding the need for additional redundant storage.
Solution Approach 2:
The patent changes the operational parameters of the ECC system by introducing erasure decoding capability. Instead of using standard ECC correction limits, the system leverages knowledge of error locations (erasure information) to modify the decoding process. This parameter change allows the existing ECC resources to correct more errors than traditionally possible, effectively increasing reliability without adding more memory resources.
3Ease of operation
If entire memory devices are declared faulty when errors occur, then error management is simplified, but memory lifespan is reduced and replacement is required
Solution Approach 1:
The patent applies local quality by treating different locations within memory devices differently based on their error history. Instead of uniformly declaring entire devices faulty, the system identifies specific locations (rows, columns, or blocks) where erasure errors have occurred and applies targeted erasure decoding only to those locations. This localized approach preserves the functional portions of memory devices, extending their operational lifespan while maintaining straightforward error management through systematic location tracking.
Solution Approach 2:
The patent implements preliminary action by maintaining erasure information that records locations of previously detected errors. This pre-established information allows the system to proactively apply erasure decoding to suspected locations before failures propagate. By preparing and storing error location data in advance, the system can quickly respond to new errors and prevent them from escalating into device-level failures, thereby extending memory lifespan without complicating error management.
Data Source
AI summary
Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.