Memory ECC Decoding With Erasure Search for Device Failure Recovery
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Solution Overview
Problem
Conventional error correction code (ECC) techniques for memory devices are inefficient in detecting and correcting errors due to single device failures, leading to uncorrectable errors and increased costs from the need for additional parity bits, which also conflict with the requirement to store metadata.
Innovation Solution
The implementation of heterogeneous interleaved Reed-Solomon (RS) coding with erasure decoding, where a single codeword is broken into two sub-codewords, one with sufficient parity for random error correction and the other for erasure correction, leveraging knowledge of erasure locations to identify faulty components and reduce decoding complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC techniques are used to detect and correct errors due to memory device failures, then reliability is improved, but parity bit requirements increase cost and complexity
Solution Approach 1:
The patent segments the single ECC decoding problem into two separate sub-codeword decoding problems. By dividing the codeword into two segments, each segment can be decoded independently with reduced complexity, while still achieving the same overall error correction capability for memory device failures.
2Reliability
If additional parity bits are added to correct entire device failures, then reliability is improved, but metadata storage capacity is reduced
Solution Approach 1:
By segmenting the codeword into two sub-codewords, the patent achieves device failure correction capability without requiring the full parity overhead of conventional single-codeword ECC. This segmentation allows more bits to be allocated to metadata storage while maintaining the same reliability level.
3Reliability
If single codeword ECC decoding is performed, then error correction is achieved, but decoding delays increase
Solution Approach 1:
The patent divides the decoding operation into two separate decoding operations on smaller sub-codewords. This segmentation reduces the computational complexity and decoding time for each operation, while the combined effect maintains the same error correction capability, thereby reducing overall decoding delays.
4Device complexity
If ECC techniques cannot detect entire device failure, then parity bit requirements are reduced, but uncorrectable errors increase
Solution Approach 1:
By segmenting the codeword into two sub-codewords with appropriate parity distribution, the patent enables detection and correction of entire device failures. Each sub-codeword contains sufficient parity information to detect failures in its corresponding segment, eliminating uncorrectable errors while keeping parity requirements manageable.
Data Source
AI summary
Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.