Memory ECC Testing Using Calibrated Error Injection
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Solution Overview
Problem
It is difficult for customers to practically test the error correction functionality of memory devices, particularly non-volatile memories like NAND flash, due to the rarity of error events and the complexity of artificially inducing errors without causing unintended issues.
Innovation Solution
A memory device uses dedicated op-codes to generate calibrated data errors during programming operations, allowing a host device to observe how the ECC engine behaves and performs by injecting controlled errors, which can be detected and corrected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction functionality is tested using traditional methods, then testing can be performed, but error events are rare and artificially inducing errors causes unintended issues
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing expected ECC results for various error patterns before actual testing. The host device prepares test data with known error patterns and pre-computes what the ECC engine should produce, so when real errors occur during testing, they can be immediately compared against predetermined expectations without causing unintended side effects
Solution Approach 2:
The patent uses an intermediary approach by introducing a controlled error injection mechanism between the test data and the ECC engine. Rather than directly testing with random or artificial errors that may cause unintended issues, the system uses predetermined error patterns as intermediaries that safely bridge the gap between test data and expected ECC behavior
2Reliability
If the number of parity bits in the error correction code is increased, then more data bit errors can be corrected, but the complexity of the error correction code increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction testing into discrete error patterns and corresponding expected results. Each error pattern is treated as a separate test case with predetermined expectations, allowing the system to verify ECC functionality incrementally rather than attempting to handle all possible error scenarios simultaneously, thus managing complexity while maintaining correction capability
3Measurement precision
If controlled errors are injected into stored data, then ECC functionality can be tested in a controlled environment, but this requires dedicated op-codes and specialized testing procedures
Solution Approach 1:
The patent applies universality by designing the error injection mechanism to work through existing memory programming interfaces. The same programming commands used for normal data storage are adapted to also support error pattern injection, allowing the ECC testing functionality to be integrated into the existing memory system without requiring entirely separate testing hardware or protocols
Data Source
AI summary
Systems, methods, and apparatus related to error correction in memory devices. In one approach, a memory device uses dedicated op-codes to generate, during programming operations, a pattern including known requested data errors. During reading operations on the memory device, the calibrated errors will be detected by the ECC engine of the memory device as read errors. This permits a host device to observe, in a controlled environment, how the ECC engine behaves and performs in a final manufactured memory product.