Memory Module ECC with Fail-Chip Detection for Chipkill Recovery
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Solution Overview
Problem
As memory device capacities increase, manufacturing memory devices with no defective memory cells becomes increasingly difficult, and existing error correction methods struggle to efficiently handle multi-bit errors and chipkill errors, leading to increased latency and circuit size due to excessive parity bits.
Innovation Solution
A memory system with an error correction circuit, fail chip detection circuit, and buffer that reads data and error correction codes, writes test patterns to detect fail chips, and recorrects errors using reduced parity bits based on the location of detected fail chips, allowing for efficient error correction and reduced ECC circuit size and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used to handle multi-bit errors and chipkill errors, then error correction capability is maintained, but latency increases and circuit size increases due to excessive parity bits
Solution Approach 1:
The patent applies preliminary action by detecting and marking fail chips before actual data operations. The memory controller performs fail chip detection during initialization or idle periods, storing the results in a fail chip information table. This pre-detection allows the error correction process to proceed more efficiently during actual data reads by already knowing which chips to exclude, thereby reducing latency without compromising error correction capability.
Solution Approach 2:
The patent extracts and removes fail chips from the error correction process. By identifying chips with permanent failures (chipkill errors) and storing their locations in a fail chip information table, the system excludes these chips from subsequent error correction calculations. This extraction reduces the number of chips that need to be processed during ECC operations, thereby reducing circuit size and latency while maintaining reliability.
2Reliability
If traditional error correction methods are used to handle multi-bit errors and chipkill errors, then error correction capability is maintained, but circuit size increases due to excessive parity bits
Solution Approach 1:
The patent extracts and removes fail chips from the error correction process. By identifying chips with permanent failures (chipkill errors) and storing their locations in a fail chip information table, the system excludes these chips from subsequent error correction calculations. This extraction reduces the number of chips that need to be processed during ECC operations, thereby reducing circuit size and latency while maintaining reliability.
Solution Approach 2:
The patent segments the memory system into functional components: normal chips and fail chips. By dividing the memory chips into these two categories and maintaining a separate fail chip information table, the system can apply different processing rules to each segment. This segmentation allows the error correction circuit to focus only on normal chips, reducing the overall circuit complexity and size while preserving error correction capability for multi-bit errors.
3Quantity of substance
If manufacturing continues with increased memory device capacities, then storage capacity increases, but the probability of defective memory cells increases making error-free manufacturing increasingly difficult
Solution Approach 1:
The patent applies beforehand cushioning by preparing redundancy mechanisms in advance to compensate for defective cells. The system includes error correction circuits and redundancy memory cells that are pre-configured to handle potential defects. When defects are detected during manufacturing or initial operation, the system can activate these pre-prepared compensation mechanisms, allowing continued operation despite manufacturing imperfections, thus enabling higher capacity devices to be manufactured with acceptable yield.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting error correction parameters based on detected defect patterns. When chipkill errors or multi-bit errors are detected, the system modifies its error correction strategy by updating the fail chip information table and adjusting which parity bits and redundancy cells are activated. This dynamic parameter adjustment allows the system to adapt to manufacturing variations and maintain reliability across different capacity levels.
Data Source
AI summary
An error correcting method of a memory system includes: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fail chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.