Memory ECC Decoding with Fault-Bit Testing for x8 DRAM
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Solution Overview
Problem
Current DRAM devices lack effective error correction for x8 devices, as they are not supported by standard error correction codes (ECC), leading to issues with correcting multiple faulty bits, which can result in data corruption and device failures.
Innovation Solution
Integration of a memory test into the ECC correction process, where a known pattern is written and read back to identify faulty bits, and this information is used in conjunction with ECC data to correct memory data, allowing for extended error correction beyond standard ECC capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ECC correction is used for x8 devices, then device complexity is reduced, but error correction capability is insufficient for multiple faulty bits
Solution Approach 1:
The patent performs a memory test before attempting ECC correction to identify faulty bits in advance. By writing a known pattern to the memory address and reading it back, the system determines which bits are defective before the actual data correction is needed, enabling more effective error correction for x8 devices
Solution Approach 2:
The patent introduces an intermediary memory test process between the ECC error detection and the correction step. This intermediate test uses a known pattern to identify specific faulty bits, providing additional information that bridges the gap between standard ECC capabilities and the need for correcting multiple faulty bits in x8 devices
2Reliability
If memory test is integrated into ECC correction, then error correction capability is extended, but processing time increases
Solution Approach 1:
The memory test using a known pattern is performed preliminarily to identify faulty bits before actual data correction. This advance identification prevents repeated testing and correction attempts, ultimately reducing total processing time despite the additional initial test step
Solution Approach 2:
The patent performs a partial memory test focused specifically on identifying faulty bits rather than a complete memory validation. By using a known pattern and comparing only the critical bits, the system achieves sufficient error correction capability without the time cost of exhaustive testing
3Quantity of substance
If x8 devices are used to reduce memory size, then density increases, but standard ECC support is unavailable leading to data corruption
Solution Approach 1:
The patent introduces an intermediary memory test process that bridges the gap between x8 device usage and reliable error correction. By inserting this test step that identifies faulty bits using a known pattern, the system enables x8 devices to achieve data integrity levels comparable to or exceeding traditional ECC-supported devices
Solution Approach 2:
The patent changes the operational parameters of x8 devices by implementing a customized error correction approach that uses a known pattern test. This parameter change allows x8 devices to operate reliably despite lacking standard ECC support, effectively adapting the error correction mechanism to the specific device architecture
Data Source
AI summary
A decoder is disclosed with error correction for memory data. The decoder's error correction is extended to additional faulty bits by integrating a memory test into the error correction to identify faulty bits in the memory data. A method for correction can include writing a known pattern to the failing address (and possibly to neighboring addresses), reading the known pattern back and comparing the read data to the written pattern to identify the failing bits. The failing bits are then used together with the error correction data to correct memory data having multiple incorrect bits or to alert other components about the failing bit locations.