Memory Controller ECC Re-Read for Fault Attack Detection
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Solution Overview
Problem
Modern IT and embedded systems face increasing threats from fault attacks, particularly laser fault injection (LFI) and electromagnetic fault injection (EMFI), which target the data/code read path in memory, and existing error detection methods like EDC and double reading incur performance penalties or area overhead.
Innovation Solution
A memory controller that re-uses existing ECC bits for error detection, re-reads data when correctable errors are detected, and incorporates reference data reads to enhance fault detection, including address decoding for error detection without correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection methods like EDC or double reading are used, then security against fault attacks is improved, but performance penalty and area overhead increase
Solution Approach 1:
The patent makes existing ECC bits serve dual purposes: their traditional error correction function and a new error detection function for security against fault attacks. By configuring the ECC decoder to detect errors and generate anomaly signals without requiring separate detection codes or multiple read operations, the system achieves enhanced security while avoiding the performance penalties and area overhead associated with EDC or double reading methods
Solution Approach 2:
The system uses its own existing ECC resources (decoder and bits) to provide self-protection against fault attacks. The ECC decoder is configured to perform both error correction and error detection functions, generating anomaly signals when errors are detected. This self-service approach eliminates the need for external security mechanisms and avoids additional performance overhead
2Reliability
If error detection methods like EDC or double reading are used, then security against fault attacks is improved, but area overhead increases
Solution Approach 1:
The patent makes existing ECC bits serve dual purposes: their traditional error correction function and a new error detection function for security against fault attacks. By configuring the ECC decoder to detect errors and generate anomaly signals without requiring separate detection codes or multiple read operations, the system achieves enhanced security while avoiding the performance penalties and area overhead associated with EDC or double reading methods
Solution Approach 2:
The patent merges the error detection function with the existing ECC error correction function. Instead of implementing separate EDC circuits or duplicate read paths, the system combines fault detection capabilities into the existing ECC decoder, allowing a single hardware component to perform both error correction and security verification functions
3Productivity
If ECC decoder detects correctable errors and returns data, then productivity is improved, but reliability may be compromised if faults are missed
Solution Approach 1:
The ECC decoder provides feedback through anomaly signals when errors are detected in read data. When correctable errors are found, the system can request re-reading of the data, and the feedback mechanism ensures that undetected faults do not compromise system reliability. This feedback loop maintains both productivity (by correcting common errors) and reliability (by detecting and flagging potential fault attacks)
Solution Approach 2:
The system performs partial error detection by focusing on detecting anomalies that indicate fault attacks rather than attempting to detect and correct all possible errors. The ECC decoder generates anomaly signals for suspected faults, allowing the system to take targeted action (such as requesting re-reads) only when necessary, thereby maintaining high productivity while ensuring reliability
Data Source
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AI summary
Various embodiments relate to a memory controller configured to read data from a memory array, including: an error correction codes (ECC) encoder configured to encode data stored in the memory array; an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and a fault controller configured to: command the memory controller to read other data from the memory array when the ECC detects an error; command the memory controller to re-read the first data from the memory array; when the ECC detects an error; compare the re-read first data to the read first data; and signal a fault attack when the re-read first data is different from the read first data.