Memory Controller ECC Layout Across Four Beats for Unknown Errors
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Solution Overview
Problem
Existing memory controllers are unable to effectively correct errors in data stored in memory modules due to limited error correction code (ECC) availability, particularly when the location of errors is unknown, leading to incomplete error correction and vulnerability to hardware faults.
Innovation Solution
A memory controller that distributes each codeword across multiple memory modules and uses at least four symbols of error correction code, spread over multiple data transfers, to enable detection and correction of single symbol errors at unknown locations, thereby reducing the impact of hardware faults and ensuring reliable data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single symbol of ECC is used in the codeword, then the ratio of message data to ECC is maximized, but the error correction capability is insufficient when error location is unknown
Solution Approach 1:
The codeword is segmented into multiple beats (temporal segments) for transmission over the interface. Each beat contains a portion of the codeword bits, and the same bit position across different beats corresponds to the same physical wire. This segmentation allows the system to use 4 symbols of ECC distributed across the beats, providing sufficient error correction capability while maintaining efficient data transmission.
2Reliability
If two symbols of ECC are used to correct errors at unknown locations, then error correction capability is improved, but the number of message data bits transmitted is reduced
Solution Approach 1:
The patent transitions from a spatial arrangement to a temporal arrangement by distributing the codeword across multiple beats in time. This allows the ECC symbols to be spread across different time slots (beats) while maintaining the same bit positions, effectively using the time dimension to achieve both high error correction capability and high data transmission rate.
3Ease of operation
If codeword bits are written to the same memory region, then memory access is simplified, but hardware faults in that region affect all bits
Solution Approach 1:
The codeword is segmented and distributed across multiple memory regions through multiple beats. Bits that would otherwise be written to the same memory region are instead distributed across different regions by writing to different beats, reducing the impact of localized hardware faults.
Solution Approach 2:
Different portions of the codeword are written to different memory regions based on their beat position. This creates local differentiation in the memory write pattern, so that a fault in one memory region affects only a limited subset of the codeword bits rather than all bits.
Data Source
AI summary
A memory controller is provided for reading and writing to and from a memory module. The memory controller implements an error correction algorithm, which calculates error correction code for message data to be written to the memory module and checks the error correction code against the message data when the data is read out of the memory module. The memory controller spreads each codeword over at least four different beats sent over the interface with the memory module, with each beat comprising a symbol of error correction code. Bits of a particular symbol of message data occupy the same positions in different beats. Since the bits of the symbols occupy the same positions in different beat, the number of bits affected by a hardware error is minimised. With four symbols of error correction code available for use in the codeword.