Memory ECC Error Testing Across Write-Read Data Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems lack effective methods to test error detection and correction performance along the full data path, including writing and reading operations, which hinders adjustments and optimizations of error correction and detection circuitry.
Innovation Solution
A memory system generates ECC bits for data and stores them in a register, writes the data and ECC bits to the memory array, and then applies error vectors to test error detection and correction performance by comparing modified data with stored ECC bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If error detection and correction testing is performed without writing data to the memory array, then testing can be simplified, but the full data path cannot be verified
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing expected ECC values in a lookup table before testing begins. During the test, these pre-computed values are compared against actual ECC values generated from data written to and read from the memory array, enabling comprehensive full data path verification without complicating the testing procedure
2Reliability
If ECC bits are stored in a register during testing, then full data path verification is enabled, but additional storage resources are consumed
Solution Approach 1:
The patent makes the register serve multiple functions: it stores ECC bits during normal operation and simultaneously serves as test data storage during error detection and correction testing. This multi-functionality allows full data path verification without requiring dedicated additional storage resources
3Reliability
If error vectors are applied to test the full data path, then comprehensive error detection is achieved, but testing time increases
Solution Approach 1:
The patent applies continuity of useful action by performing error detection and correction testing during regular memory write and read operations. The test leverages the existing data flow through the memory system, allowing comprehensive error detection without requiring separate dedicated test time periods
Data Source
AI summary
Methods, systems, and devices for systems and techniques for error testing are described. As part of a first write operation, a memory system may write data and associated error correction code (ECC) bits to a memory array. In accordance with a first portion of a test, the memory system may store a copy of the ECC bits to a register of the memory system. As part of a second write operation, the memory system may write an error vector to the memory array. In accordance with a second portion of the test, the memory system may store the previously-stored ECC bits from the register to the memory array. The memory system may subsequently access the error vector and the ECC bits from the memory array to support verification of error correction and detection performance of the memory system.