Memory ECC Scheme Using Grouped LDPC and BCH Decoding
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Solution Overview
Problem
Existing memory systems face high error floors in LDPC decoding operations, leading to inefficient BCH decoding overhead due to frequent execution of error correction for each codeword that fails LDPC decoding, resulting in increased encoder/decoder circuitry and reduced performance.
Innovation Solution
Implementing a method where only one in four LDPC codewords failing LDPC decoding triggers a BCH decoding operation, using concatenated LDPC codewords with BCH parity bits to reduce the overall error floor and BCH overhead, by forming a BCH codeword based on the summation of four LDPC codewords, thereby reducing the need for frequent BCH decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCH decoding operation is executed for every LDPC codeword that fails LDPC decoding, then error correction capability is improved, but BCH decoding overhead increases four times
Solution Approach 1:
The patent segments the error correction process by dividing LDPC codewords into groups of four and applying BCH decoding only to groups containing failed codewords, rather than processing every failed codeword individually. This segmentation reduces the frequency of BCH decoding operations from 4 times to 1 time per group, directly addressing the overhead problem while maintaining error correction capability through selective processing.
Solution Approach 2:
The patent applies partial action by executing BCH decoding only when necessary (when LDPC decoding fails) rather than for every codeword. By performing BCH decoding on a subset of codewords (those that failed LDPC decoding) rather than all codewords, the system reduces unnecessary processing overhead while maintaining adequate error correction for the failed cases.
2Reliability
If BCH decoding is executed frequently for each failed LDPC codeword, then error floor is reduced, but encoder/decoder circuitry complexity increases
Solution Approach 1:
The patent merges multiple LDPC codewords into a single BCH codeword by concatenating four LDPC codewords with BCH parity bits. This merging approach allows the system to process groups of failed codewords together through a single BCH decoding operation, reducing the number of separate decoding circuits needed and simplifying the overall encoder/decoder architecture while maintaining error floor performance.
Solution Approach 2:
The patent creates a universal BCH decoding mechanism that can handle multiple failed LDPC codewords through a single decoding operation. By designing the BCH code to work on concatenated groups of LDPC codewords, the system achieves multi-functionality where one BCH decoder can serve the role of multiple individual decoders, reducing circuitry complexity while maintaining comprehensive error correction capability.
3Loss of time
If BCH parity bits are concatenated with LDPC codewords, then BCH overhead is reduced by four times, but codeword formation complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing BCH parity bits that can be concatenated with groups of four LDPC codewords. This preliminary preparation of parity bits allows the system to efficiently form BCH codewords when needed, reducing the computational overhead during actual decoding operations while the initial complexity of parity bit generation is performed once during code setup rather than repeatedly during operation.
Data Source
AI summary
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.