Memory ECC Engine with H-Matrix Codes to Prevent Miscorrection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory capacity increases, it becomes increasingly difficult to produce memory chips with no defective memory cells, and existing error correction circuits may cause miscorrection during error correction processes.
Innovation Solution
A memory system incorporating an ECC engine that generates and uses a specific H matrix to perform logical operations on write data, generating multiple error correction codes, and corrects errors during read operations using syndromes, while preventing miscorrection by employing Galois fields and companion matrices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but the probability of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by generating error correction codes during the write operation before data is stored in memory. The ECC engine performs logical operations on write data and the H matrix to generate first and second error correction codes, which are then stored together with the write data. This preliminary error correction preparation enables future error detection and correction without requiring actual errors to occur first.
Solution Approach 2:
The patent introduces an intermediary mechanism - the error correction code - that mediates between the stored data and potential errors. The H matrix serves as an intermediary structure that transforms write data into error correction codes through logical operations. During read operations, the same H matrix structure enables syndrome generation to detect and correct errors, acting as a bridge between data storage and error correction functions.
2Reliability
If existing error correction circuits are used, then error correction capability is provided, but miscorrection occurs during error correction processes
Solution Approach 1:
The patent segments the error correction code into two distinct parts: a first error correction code and a second error correction code. This segmentation is achieved through the dual-matrix structure of the H matrix, which generates separate codes that can be independently processed. During error correction, this segmentation allows the system to generate syndromes for each code separately, enabling more precise error location identification and reducing miscorrection by distinguishing between different error locations and types.
3Reliability
If redundancy memory cells are used to repair defective cells, then defective memory cells can be replaced, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical approach of physically replacing defective memory cells with redundancy cells with a mathematical/software-based error correction system. Instead of managing physical redundancy and performing complex cell swapping operations, the system uses the H matrix and error correction codes to detect and correct errors through logical operations and syndrome generation. This substitution eliminates the need for complex redundancy management hardware and procedures while maintaining reliability.
Data Source
AI summary
A memory system may include a memory core; and an ECC engine configured to, during a write operation, perform a logical operation on an M-bit write data and an H matrix, and generate an N-bit first error correction code and an N-bit second error correction code to be stored in the memory core together with the write data, where N is an integer of 2 or more and M is a multiple of N. The H matrix may include an upper matrix having a size of N*(M+2N) and a lower matrix having a size of N*(M+2N), the lower matrix may include M/N Tk companion matrices each having a size of N*N, and k of the Tk companion matrices may have values which are positive integers different by N or more for each companion matrix.