Two-Layer Memory ECC Using Hamming and Golay Codes
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Solution Overview
Problem
Memory devices often experience higher failure rates than can be corrected with existing two or three bit error correction methods, leading to discarded devices and reduced yields during manufacturing.
Innovation Solution
Implementing a two-layer quad bit error correction system using Hamming and Golay codes, where data is encoded with Hamming and Golay code bits before storage, and decoded using Golay and Hamming correction vectors to correct errors, allowing for up to quad bit error correction while maintaining compatibility with industry standard interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two bit error correction is implemented, then device complexity is reduced, but reliability deteriorates because higher failure rates cannot be corrected
Solution Approach 1:
The error correction system is segmented into two distinct layers: a first layer using Hamming codes for single bit error correction, and a second layer using Golay codes for additional error correction. This segmentation allows the system to achieve quad bit error correction capability while managing complexity through modular organization of correction functions.
Solution Approach 2:
The patent transitions from traditional single-layer error correction to a two-dimensional layered correction architecture. The first layer handles single bit errors independently, while the second layer provides additional correction capacity for multiple bit errors, creating a dimensional expansion in the error correction approach that enhances reliability without linearly increasing complexity.
2Reliability
If quad bit error correction is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The quad bit error correction capability is achieved through segmentation into hierarchical layers: the first layer provides baseline single bit correction using Hamming codes, and the second layer adds Golay code-based correction for multiple bit errors. This segmentation enables the system to handle up to four bit errors while organizing complexity into manageable modular components rather than a monolithic complex system.
3Productivity
If more bits are corrected, then manufacturing yields increase, but device complexity increases
Solution Approach 1:
The error correction system is divided into functional segments where the first layer handles common single bit errors that occur frequently in manufacturing variations, and the second layer addresses less frequent multiple bit errors. This segmentation enables recovery of marginally defective devices that would otherwise be discarded, thereby improving manufacturing yields while keeping each segment's complexity manageable.
Solution Approach 2:
The system changes the parameter of error correction capacity from traditional single or double bit correction to quad bit correction by introducing a second correction layer. This parameter change allows devices with higher defect rates to be rescued and included in production, directly improving manufacturing yields without requiring complete redesign of the base correction system.
Data Source
AI summary
In some examples, a memory device may be configured to provide quad bit error correction circuits. For example, the memory device may be equipped with a two layer error correction circuit. In some cases, the first layer may utilized one or more Hamming coders and the second layer may utilize one or Golay coders. In some examples, the Golay coders may be grouped into sets of Golay coders.