Memory Controller ECC for Hard Failure and Multi-Bit Error Detection
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Solution Overview
Problem
Existing error correction code systems face challenges in effectively detecting and correcting both hard and soft errors in electronic systems, particularly in identifying multi-bit errors and component failures, which can lead to data corruption.
Innovation Solution
A memory controller with a check bit encoder circuit and a check/correct circuit that generates and uses a specific arrangement of check bits, including row and inner check bits, to detect errors and identify hard failures by performing memory read/write operations, and utilizes Galois Field arithmetic to correct single component failures and detect multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC schemes are used to detect and correct bit errors, then single bit errors can be corrected, but multi-bit errors and hard component failures cannot be effectively detected
Solution Approach 1:
The patent segments the encoded data block into an array of R rows and N columns, with check bits organized in a first column and data bits in subsequent columns. This segmentation enables the system to detect multi-bit errors by examining error patterns across multiple rows, while maintaining a structured approach that manages complexity through systematic organization of check bits and data bits.
Solution Approach 2:
The patent transitions from traditional single-dimensional error checking to a two-dimensional array structure where data bits are arranged in columns and check bits in rows. This dimensional change enables detection of multi-bit errors by analyzing error syndromes across multiple dimensions, allowing the system to identify patterns that indicate hard failures rather than simple bit flips.
2Reliability
If the number of check bits is increased to detect more bit errors, then more errors can be detected and corrected, but the overhead and system complexity increase
Solution Approach 1:
The patent makes the check bits multi-functional by using them for both traditional single-bit error correction and multi-bit error detection. The same check bits in the first column serve dual purposes: generating syndromes for single-bit correction and participating in multi-dimensional error pattern analysis for multi-bit detection. This universality reduces the need for additional dedicated check bits while expanding error detection capabilities.
3Reliability
If hard failure detection is added to the ECC system, then component failures can be identified, but the system complexity and number of operations increase
Solution Approach 1:
The patent enables the ECC system to self-diagnose hard failures by using its existing check bits and syndrome generation capability. When multi-bit errors are detected through the multi-dimensional error analysis, the system automatically performs additional memory read/write operations to identify whether the cause is a hard component failure, eliminating the need for separate dedicated hard failure detection circuitry.
Data Source
AI summary
In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled to the check/correct circuit. The check bit encoder circuit is configured to generate a corresponding encoded data block comprising the data block, a first plurality of check bits, and a second plurality of check bits. The check/correct circuit is configured to detect an error in the encoded data block responsive to the first check bits, the second check bits, and the data block within the encoded data block, which is logically arranged as an array of R rows and N columns, wherein R and N are positive integers. Each of the first check bits covers a respective row of the array, and the check/correct circuit is configured to generate a first syndrome corresponding to the first plurality of check bits. A presence of more than one binary one in the first syndrome indicates a multi-bit error. Responsive to detecting the multi-bit error, the hard failure detection circuit is configured to perform a plurality of memory read/write operations to the memory locations in which the encoded data block is stored to identify a hard error failure in the memory.