Memory ECC with Known Data for High Bit Error Retrieval
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Solution Overview
Problem
Conventional memory devices face reliability issues as the bit error rate increases, causing error correction codes to fail in decoding data, leading to premature degradation of memory cells and reduced storage capabilities.
Innovation Solution
Combining user data with known data patterns to enhance error correction capabilities, allowing the error correction code to tolerate higher bit error rates and extend the useful life of memory devices by reducing the effective error rate and minimizing wear on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code with predetermined code rate is used to retrieve data from memory device, then data reliability is improved, but the system fails when bit error rate exceeds the correction capability threshold
Solution Approach 1:
The patent dynamically adjusts the code rate of the error correction code based on the observed bit error rate. When the bit error rate is low, a lower code rate is used to maximize storage capacity. When the bit error rate increases beyond the correction capability of the predetermined code rate, the system switches to a higher code rate to maintain data reliability. This dynamic adaptation resolves the contradiction by making the error correction system flexible rather than fixed.
Solution Approach 2:
The system changes the parameter of code rate from a fixed predetermined value to a variable parameter that adapts to the actual bit error rate conditions. By monitoring the bit error rate and adjusting the code rate accordingly, the system can handle varying error conditions effectively, resolving the contradiction between maintaining high reliability and adapting to different error rates.
2Productivity
If memory cells are continuously programmed and erased to store and retrieve data, then storage functionality is maintained, but memory cell wear increases leading to premature degradation
Solution Approach 1:
The patent incorporates known data patterns during the programming phase, allowing the error correction system to anticipate and prepare for potential errors. By pre-programming known patterns and pre-calculating their error correction requirements, the system can faster detect and correct errors during retrieval, reducing the need for repeated read-verify-rewrite cycles that would increase wear on memory cells.
Solution Approach 2:
The error correction system uses the known data patterns to self-verify and self-correct errors without requiring external intervention or repeated access cycles. The predetermined error correction codes are designed to work with the known patterns, allowing the system to automatically detect and correct errors during normal operations, thereby reducing additional programming/erasing cycles and extending memory device lifespan.
3Device complexity
If error correction code with fixed code rate is applied, then implementation simplicity is maintained, but error correction capability is insufficient when bit error rate exceeds threshold
Solution Approach 1:
The patent segments the error correction process into multiple stages: first applying a predetermined error correction code with a fixed code rate for basic error correction, then monitoring the bit error rate, and only when necessary, switching to a different code rate. This segmentation allows the system to maintain simple fixed-rate implementation for normal operations while having the capability to adapt to higher error rates when needed.
Solution Approach 2:
The error correction system is designed to handle multiple code rates using a universal error correction framework. Rather than implementing separate error correction systems for different code rates, the patent uses a multi-functional error correction capability that can operate with various code rates, maintaining implementation efficiency while providing adaptability to different error conditions.
Data Source
AI summary
A memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.