Memory ECC Latency Control for Synchronized Parallel Data Paths
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Solution Overview
Problem
Existing memory devices face challenges in managing latency differences between data and error correction codes during transmission, particularly at varying frequencies and operation types, which affects system efficiency and circuit complexity.
Innovation Solution
The implementation of a latency controller that variably controls the difference in latency between data and error correction codes by using separate data and error correction drivers, buffers, and latency controllers, allowing for programmable latency adjustments based on transmission frequency and operation type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed latency settings are used for data and error correction code transmission, then device complexity is reduced, but transmission efficiency deteriorates in high-speed environments with varying frequencies
Solution Approach 1:
The patent implements a latency controller that dynamically adjusts the latency of error correction code transmission based on the transmission frequency of data. The controller receives frequency information from the memory controller and varies the latency accordingly, enabling the system to adapt to different operating conditions and maintain optimal transmission efficiency without requiring complex manual configuration
Solution Approach 2:
The patent changes the latency parameter of error correction code transmission based on the transmission frequency of data. By adjusting the latency parameter dynamically according to frequency conditions, the system optimizes transmission efficiency for high-speed operations while maintaining compatibility with standard memory controllers that do not provide frequency information
2Speed
If separate parallel channels are used for data and error correction codes, then transmission speed is improved, but latency synchronization becomes more difficult
Solution Approach 1:
The patent introduces a latency controller as an intermediary component between the error correction code generator and the transmission interface. This controller mediates the timing relationship between data and error correction code transmission by adjusting the latency of error correction codes based on the data transmission frequency, thereby synchronizing the parallel channels without compromising transmission speed
Solution Approach 2:
The patent dynamically adjusts the latency of error correction code transmission to match the data transmission timing. By making the latency variable rather than fixed, the system maintains synchronization between parallel data and error correction code channels while preserving the speed benefits of parallel transmission
3Reliability
If latency is increased to synchronize data and error correction codes, then data integrity is improved, but transmission delay increases
Solution Approach 1:
The patent changes the latency parameter dynamically based on transmission frequency rather than using a fixed increased latency. By adjusting the latency parameter to match actual transmission conditions, the system ensures proper synchronization for data integrity while minimizing unnecessary transmission delays that would occur with fixed latency increases
Data Source
AI summary
In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.