Memory ECC Architecture With Layered Codes for High-Capacity Reliability
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Solution Overview
Problem
As memory capacity increases, it becomes challenging to fabricate error-free memory systems, and existing error correction methods in memory systems are inefficient, particularly due to inferior error detection and correction capabilities in memory error correction circuits compared to system error correction circuits.
Innovation Solution
A memory system that includes a memory controller and memory with error correction code generation circuits to generate and store multiple error correction codes, allowing for improved error correction efficiency by enhancing the error detection and correction capabilities of the memory error correction circuit to match or exceed those of the system error correction circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but manufacturing precision deteriorates due to difficulty in fabricating error-free memory cells
Solution Approach 1:
The patent applies preliminary action by generating error correction codes during the write operation before data is stored in the memory. The memory controller generates a first system ECC and second system ECC, and the memory generates first memory ECC and second memory ECC based on the write data and second system ECC. This preliminary error correction preparation ensures that even if manufacturing defects occur in high-capacity memory, the data can be corrected during read operations.
2Quantity of substance
If memory capacity is increased, then storage capability is improved, but reliability deteriorates due to higher likelihood of defective memory cells
Solution Approach 1:
The patent prepares error correction codes in advance during the write operation. The memory controller generates system ECC codes, and the memory generates additional memory ECC codes based on the write data and second system ECC. This preliminary preparation ensures that when data is read, errors from manufacturing defects can be immediately corrected, maintaining reliability in high-capacity memory systems.
Solution Approach 2:
The patent implements beforehand cushioning by storing multiple layers of error correction codes (first system ECC, second system ECC, first memory ECC, second memory ECC) alongside the data in the memory core. These redundant codes act as a cushion against potential errors, ensuring that even if manufacturing defects occur in high-capacity memory, the data integrity is protected through multiple correction opportunities during read operations.
3Reliability
If error correction capability of memory circuit is enhanced, then reliability is improved, but device complexity increases due to additional correction circuits
Solution Approach 1:
The patent merges error correction functions by having the memory generate error correction codes based on both the write data and the second system ECC from the memory controller. This combining approach allows the memory's error correction circuit to work synergistically with the system-level ECC, providing enhanced reliability without requiring completely separate correction systems, thus managing complexity more effectively.
Data Source
AI summary
A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code and a second system error correction code based on write data; and a memory including: a memory error correction code generation circuit configured to generate a first memory error correction code based on the write data transferred from the memory controller, and generate a second memory error correction code based on the second system error correction code transferred from the memory controller, and a memory core configured to store the write data, the first system error correction code, the second system error correction code, the first memory error correction code and the second memory error correction code.