Non-Volatile Memory ECC Level Selection for Deteriorated Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face challenges in error correction due to severe memory cell deterioration, leading to increased latency and reduced reliability in data recovery, as existing error correction codes struggle to correct errors effectively when the degree of deterioration is high.
Innovation Solution
A controller and storage device system that includes an error correction circuit capable of selecting an optimal error correction decoding level based on predicted memory cell distribution, using side information from non-volatile memory devices to perform adaptive defense code operations, such as on-chip valley search and error correction, to reduce latency and improve data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed error correction decoding level is used, then the error correction process is simple and fast, but it cannot effectively correct errors when memory cell deterioration is severe
Solution Approach 1:
The patent implements dynamic error correction decoding by selecting different ECC decoding levels (first, second, or third level) based on the predicted memory cell distribution. The controller adapts the decoding complexity to the actual error conditions, using stronger decoding only when necessary, thus resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The system changes the error correction decoding parameter (decoding level) based on the predicted distribution of memory cells. By adjusting the decoding level according to the predicted error rate and distribution, the system achieves effective error correction while avoiding unnecessary complexity when errors are few.
2Reliability
If read retry operations are performed using different sensing techniques, then error correction capability is improved, but latency increases
Solution Approach 1:
The system performs preliminary prediction of memory cell distribution before executing the full error correction process. This preliminary action allows the controller to anticipate the error conditions and select the appropriate ECC decoding level in advance, avoiding unnecessary read retry operations and reducing overall latency while maintaining data recovery reliability.
3Adaptability or versatility
If multiple error correction decoding levels are implemented, then adaptability to different deterioration conditions is improved, but processing time increases
Solution Approach 1:
The system dynamically selects among multiple ECC decoding levels based on the predicted memory cell distribution, implementing adaptability only when needed. The controller adjusts the decoding level in real-time according to the predicted error conditions, achieving high adaptability without the constant processing overhead of evaluating multiple decoding levels for every read operation.
Data Source
AI summary
A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.