Memory ECC LLR Table Switching for Faster LDPC Decoding
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Solution Overview
Problem
Current memory systems face challenges in efficiently correcting errors in data read from memory devices due to variations in cell transistor properties, leading to inaccurate data retrieval and increased error correction times.
Innovation Solution
The memory system employs an error correction code (ECC) circuit that uses a combination of hard-bit and soft-bit decoding, along with Low-Density Parity-Check (LDPC) coding, to detect and correct errors by converting log-likelihood ratio (LLR) values through adaptive LLR table adjustments, optimizing read voltage conditions to improve error correction accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If adaptive LLR table adjustments are used to improve error correction accuracy, then data retrieval accuracy is improved, but device complexity increases
Solution Approach 1:
The system pre-prepares multiple LLR tables with different conversion relationships before actual data reading operations. When errors occur during data retrieval, the controller can immediately switch to a pre-configured alternative LLR table without performing complex real-time adjustments, thereby improving data retrieval accuracy while avoiding the complexity of dynamic table generation
Solution Approach 2:
The error correction mechanism dynamically selects among multiple LLR tables based on the specific error conditions detected during data reading. The controller adjusts which LLR table is used by evaluating error patterns and switching between different conversion relationships, enabling adaptive error correction without requiring a single complex fixed mechanism
2Measurement precision
If multiple LLR tables are used for optimal error correction, then error correction accuracy is improved, but decoding time increases
Solution Approach 1:
Multiple LLR tables are pre-configured with different conversion relationships before operation. When data is read from the memory device, the controller can immediately apply the appropriate pre-prepared table based on detected error patterns, avoiding the time-consuming process of generating or adjusting tables in real-time during decoding operations
Solution Approach 2:
The error correction process is segmented into distinct phases: error detection phase where error patterns are identified, and correction phase where the appropriate pre-prepared LLR table is selected and applied. This segmentation allows the system to efficiently navigate between multiple tables without performing exhaustive searches, reducing overall decoding time while maintaining high correction accuracy
3Reliability
If hard-bit and soft-bit decoding combination is used, then error detection capability is improved, but processing complexity increases
Solution Approach 1:
The decoding process is divided into two distinct segments: hard-bit decoding that processes definitive bit values, and soft-bit decoding that processes probabilistic bit information. Each segment uses specialized processing logic optimized for its data type, and the results are combined to achieve superior error detection capability while keeping each individual processing module relatively simple and manageable
Data Source
AI summary
In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.