Semiconductor Memory Error Correction Loop for Data Retention

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Solution Overview

Problem

Semiconductor memory devices face challenges in maintaining data retention characteristics due to increased bit errors and threshold voltage distribution widening over time, leading to potential incorrect data readouts.

Innovation Solution

Implementing an error correction loop (ECC) that increments the number of correctable bits and performs repeated error correction operations until bit errors are minimized, with the ECC count being used to determine when corrected data is programmed back to memory cells, thereby enhancing data retention and reducing the adverse effects of program/erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If repeated ECC operations are performed to correct bit errors, then data retention characteristics are improved, but the duration of refresh operations increases

Engineering Contradiction:
Improvedata retention characteristicsVSAvoidduration of refresh operations
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic adjustment of the maximum number of correctable bits based on the number of bit errors detected. When bit errors exceed the initial threshold, the system increments the maximum number of correctable bits and performs additional ECC iterations. This dynamic adaptation allows the system to extend data retention protection only when needed, avoiding unnecessary refresh operations and reducing overall time loss while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the maximum number of correctable bits is increased to handle more bit errors, then data retention is improved, but the complexity of the error correction loop increases

Engineering Contradiction:
Improvedata retentionVSAvoiderror correction loop complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a dynamic error correction loop that adjusts the maximum number of correctable bits based on detected bit error counts. The system starts with an initial maximum number of correctable bits and only increments this value when bit errors exceed the current threshold. This dynamic approach allows the system to handle varying error conditions without maintaining a constantly complex correction loop, thereby managing complexity while improving data retention.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism where the number of bit errors detected during ECC operations is monitored and used to adjust the maximum number of correctable bits. When bit errors exceed the current maximum, the system increments the maximum and continues correction attempts. This feedback-driven adaptation allows the error correction loop to respond to actual error conditions, improving data retention without requiring a predetermined complex correction structure for all possible error scenarios.

Inventive Principle:
Principle #23Feedback

3Reliability

If multiple ECC iterations are performed to correct persistent bit errors, then data retention characteristics are enhanced, but the number of operations required increases

Engineering Contradiction:
Improvedata retention characteristicsVSAvoidnumber of operations
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a dynamic error correction strategy where the maximum number of correctable bits is incremented only when bit errors exceed the current threshold. This dynamic adjustment ensures that additional ECC iterations are performed only when necessary to address persistent errors, rather than executing a fixed number of operations regardless of error conditions. Consequently, the system enhances data retention characteristics when needed while minimizing unnecessary operations and maintaining productivity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9213592B2Semiconductor memory device and method of operating the same
Publication Date: 2015.12.15 MIMIRIP LLC
  • US9213592B2 patent drawing
  • US9213592B2 patent drawing
  • US9213592B2 patent drawing

AI summary

Semiconductor memory device and method of operating same includes reading data stored in memory cells of a page; performing an error correction loop (ECC loop) including performing an error checking and correcting operation (ECC) on the read data; determining a number of bit errors in the read data; and when the number of bit errors is greater than a maximum number of correctable bits, incrementing the number of ECC iterations (ECC count) and increasing the maximum number of correctable bits; storing the ECC count until the number of bit errors is less than the maximum number of correctable bits; and programming corrected data to the memory cells when the stored ECC count is more than preset number.