Memory ECC Layout for LSB Error-Prone Data Pages
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Solution Overview
Problem
As memory cell density increases, maintaining the reliability of information stored in memory devices becomes challenging due to higher probabilities of error occurrence, particularly in bit positions that are more prone to changes, such as the least significant bits (LSBs), which are more error-prone compared to most significant bits (MSBs.
Innovation Solution
The solution involves allocating more error correction code (ECC) bits to data stored in bit positions that are more likely to have errors, determined by analyzing bit patterns, and organizing data and ECC in a way that more ECC is allocated to pages containing LSBs, which are more error-prone, while less ECC is allocated to pages containing MSBs, using techniques like low-density parity-check (LDPC) coding and generator matrices to generate and store ECC sets accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to improve storage capacity, then the storage capacity is improved, but the reliability of stored information deteriorates due to higher error occurrence probabilities
Solution Approach 1:
The patent applies local quality by differentiating error correction protection levels based on bit position characteristics. LSBs (least significant bits) are identified as more error-prone and are allocated more ECC bits for protection, while MSBs (most significant bits) receive fewer ECC bits. This non-uniform distribution of error correction resources matches the local error susceptibility of different bit positions, resolving the contradiction between maintaining high storage density and ensuring information reliability.
2Reliability
If more ECC bits are allocated to protect error-prone bit positions, then the reliability is improved, but the device complexity increases due to differential ECC organization
Solution Approach 1:
The patent segments the data storage structure into different pages based on bit position characteristics. Specifically, it creates first pages containing MSBs with fewer ECC bits and second pages containing LSBs with more ECC bits. This segmentation allows the system to manage complex differential ECC requirements by organizing them into distinct, manageable page structures, thereby reducing overall device complexity while maintaining enhanced error correction capability where needed.
3Reliability
If differential ECC allocation is implemented to address LSB error-proneness, then the error correction capability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-determining which bit positions are more error-prone (LSBs) and pre-allocating appropriate ECC bits to protect them before data is actually stored. The system analyzes bit patterns to identify error susceptibility and establishes the differential ECC allocation structure in advance. This preliminary organization simplifies the manufacturing process by providing clear, pre-defined rules for ECC allocation rather than requiring complex real-time adjustments during manufacturing.
Data Source
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AI summary
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.