Memory ECC Bit Distribution for Metadata Allocation
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Solution Overview
Problem
Increasing memory device density and operating speeds lead to higher runtime errors, with traditional architectures using all ECC bandwidth, leaving no bits available for system-level purposes other than error correction, posing challenges in providing single device data correction and metadata usage.
Innovation Solution
The implementation of split line access, which splits data into sub-portions across multiple memory resources, reducing the number of ECC bits needed for error correction and freeing up memory capacity for metadata usage, by distributing ECC bits across multiple memory devices, allowing for the use of additional bits for metadata.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional architectures use all available ECC bandwidth for error correction, then error correction capability is improved, but no bits are available for system-level purposes such as metadata
Solution Approach 1:
The patent divides the memory system into multiple independent memory devices, where each device handles a portion of the data and requires its own ECC bits. By segmenting the data across multiple devices, the total ECC overhead is distributed and reduced compared to protecting all data from a single device, thereby freeing up bits for metadata while maintaining error correction capability.
2Productivity
If memory device density and operating speeds are increased, then data bandwidth per transaction is improved, but runtime errors increase
Solution Approach 1:
The patent segments data into multiple portions stored across different memory devices, with each portion protected by its own ECC mechanism. This segmentation allows the system to handle higher data volumes and speeds while maintaining error correction capability for each segment, thereby managing runtime errors effectively despite increased density and operating speeds.
Solution Approach 2:
The patent changes the ECC configuration parameters by allocating different numbers of ECC bits to different memory devices based on their specific error rates and data importance. This adaptive parameter adjustment allows the system to optimize error correction capability for high-speed, high-density operations while freeing up bits for metadata.
3Reliability
If all bits are allocated to ECC for single device data correction, then SDDC capability is improved, but capacity for metadata is reduced to zero
Solution Approach 1:
The patent segments data across multiple memory devices, where each device stores a portion of the data and its corresponding ECC bits. This segmentation reduces the total ECC bits needed compared to protecting all data from a single device, thereby freeing up memory capacity for metadata while maintaining SDDC capability for each segment.
Solution Approach 2:
The patent adjusts the ECC bit allocation parameters for each memory device based on the desired level of protection and available capacity. By optimizing these parameters, the system achieves adequate error correction capability while freeing up sufficient bits for metadata storage.
Data Source
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AI summary
A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N-M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.