Memory ECC Metadata Partition for Lower-Cost Error Correction
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Solution Overview
Problem
Existing error correction schemes in computing devices are inefficient and costly, particularly due to the use of high-density on-chip SRAM for system-level ECC, which is expensive and prone to soft errors, and existing link ECC schemes do not effectively integrate with memory array ECCs, leading to system complexity and increased cost.
Innovation Solution
A system ECC scheme that shares signal connections with link ECC functions, integrating system, array, and link ECCs within memory devices to reduce complexity and cost while maintaining error detection and correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-density on-chip SRAM is used for system-level ECC, then error detection and correction capability is improved, but system cost increases and the system becomes more prone to soft errors
Solution Approach 1:
The patent merges system ECC and link ECC functions into a single integrated ECC scheme. The memory device performs both system-level error correction (for data stored in memory array) and link-level error correction (for data transmitted between host and memory) using unified logic circuits, eliminating the need for separate high-density on-chip SRAM resources and reducing overall system complexity and cost while maintaining comprehensive error protection
Solution Approach 2:
The integrated ECC scheme provides multi-functionality by enabling the same ECC logic to serve dual purposes: protecting data integrity within the memory array (system ECC) and protecting data integrity during transmission between host and memory (link ECC). This universal approach eliminates redundant components and reduces system cost while improving reliability across multiple error-prone interfaces
2Reliability
If separate on-chip SRAM is used for system ECC, then error correction is achieved, but resource overhead increases
Solution Approach 1:
The patent combines system ECC and link ECC resources into a single integrated structure, eliminating duplicate on-chip SRAM allocations. The unified ECC logic shares computational resources and storage elements between system and link functions, significantly reducing the total quantity of on-chip resources required while maintaining full error correction capability for both data paths
3Device complexity
If system ECC and link ECC are integrated, then system complexity is reduced and cost decreases, but error detection and correction capability must be maintained
Solution Approach 1:
The patent merges system ECC and link ECC into a single integrated scheme that reduces device complexity by eliminating separate logic circuits and control mechanisms. The unified ECC architecture consolidates multiple error correction functions into one coherent system, simplifying the overall device structure while maintaining comprehensive error detection and correction capabilities through coordinated operation of the integrated logic
Solution Approach 2:
The integrated ECC scheme achieves multi-functionality by designing universal logic circuits that can perform both system ECC operations (protecting memory array data) and link ECC operations (protecting transmission data). This universal approach maintains robust error detection and correction capability across different data paths while reducing system complexity through resource sharing and functional integration
Data Source
AI summary
Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.