Semiconductor Memory ECC Grouping for Miscorrection Detection

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Solution Overview

Problem

Conventional semiconductor memory devices cannot detect and correct miscorrected bits caused by error bits within their error correction ability, leading to undetected errors when error bits exceed the correction capacity of an ECC code word group.

Innovation Solution

The semiconductor memory device generates first and second check bits to divide error correcting code words into multiple groups, allowing miscorrected bits to be disposed in another ECC code word group rather than the original, enabling external detection and correction of errors beyond the initial ECC code word group's correction capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction is performed using conventional ECC code word groups, then error bits within correction capacity can be corrected, but miscorrected bits cannot be detected when error bits exceed correction capacity

Engineering Contradiction:
Improveerror correction capabilityVSAvoidundetected miscorrected bits
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The ECC code word is divided into multiple ECC code word groups, each capable of independent error correction. This segmentation allows the system to handle error bits that exceed the correction capacity of a single code word group by distributing them across multiple groups, thereby preventing miscorrected bits while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the ECC code word is divided into multiple ECC code word groups, then miscorrected bits can be detected and corrected externally, but the device complexity increases

Engineering Contradiction:
Improvedetection of miscorrected bitsVSAvoidECC code word division structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ECC code word is divided into multiple ECC code word groups, each capable of independent error correction. This segmentation allows the system to handle error bits that exceed the correction capacity of a single code word group by distributing them across multiple groups, thereby preventing miscorrected bits while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each ECC code word group is designed with universal error correction capability, allowing any group to correct error bits independently. This multi-functionality enables the system to detect and correct miscorrected bits externally while maintaining a relatively simple internal structure, as each group operates independently with the same correction mechanism.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10140176B2Semiconductor memory device, memory system including the same, and method of error correction of the same
Publication Date: 2018.11.27 SAMSUNG ELECTRONICS CO LTD
  • US10140176B2 patent drawing
  • US10140176B2 patent drawing
  • US10140176B2 patent drawing

AI summary

An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively. For each parity generator matrix group of the first parity generator matrix, a result value of a bit-by-bit exclusive OR (XOR) operation performed on any two columns included in the parity generator matrix group is equal to a column number of a column that is not included in the parity generator matrix group. Thus, when a first ECC code word group, from among the plurality of ECC code word groups, includes error bits, a miscorrected bit that would be caused by the error bits as a result of performing an error correction operation on the first ECC code word group is located in an ECC code word group other than the first ECC code word group.