Memory ECC Mode Switching for Capacity and Reliability Tradeoffs
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Solution Overview
Problem
As memory capacity increases, manufacturing memories without failed memory cells becomes challenging, and existing error correction methods are inefficient, necessitating improved error correction techniques in memory systems.
Innovation Solution
Implementing a dual error correction mode in memory systems using a first error correction code with a large bit number for high correction capability and a second error correction code with a small bit number for low correction capability, along with dedicated parity generation and correction circuits for efficient error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of memory cells are integrated to increase memory capacity, then memory capacity increases, but the likelihood of failed memory cells increases
Solution Approach 1:
The patent applies preliminary action by generating error correction codes (ECC) during the write operation before data is stored in memory. The ECC generation circuit calculates parity bits and stores them alongside the data, so that error correction can be performed during subsequent read operations without requiring additional processing time. This preliminary preparation of correction data enables efficient error handling while maintaining high memory capacity.
2Reliability
If error correction codes with large bit numbers are generated to improve error correction capability, then error correction capability improves, but memory resource consumption increases
Solution Approach 1:
The patent implements dynamic error correction mode selection that adapts to different operational requirements. The system can switch between first error correction mode (using full ECC_L codes for maximum reliability) and second error correction mode (using reduced ECC_S codes for lower resource consumption). This dynamic adjustment allows the system to optimize the balance between error correction capability and memory resource usage based on actual needs, such as using stronger correction for critical data and weaker correction for less critical operations.
Solution Approach 2:
The patent changes the parameter of error correction code strength by providing two different H matrices with different numbers of parity bits. The first H matrix generates ECC_L codes with more parity bits for higher error correction capability, while the second H matrix generates ECC_S codes with fewer parity bits for reduced memory overhead. By selecting appropriate H matrices based on operational mode, the system dynamically adjusts the parameter of correction strength to match requirements.
Data Source
AI summary
A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.