Multi-Channel Memory ECC Layout for Faster Multi-Bit Correction
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Solution Overview
Problem
High-precision semiconductor memory systems require advanced error correction codes to handle multiple-bit errors effectively, but existing codes increase die size and processing time, which is undesirable for high-speed and compact applications.
Innovation Solution
The implementation of multi-channel error correction in semiconductor devices, where data bits are distributed across channels with separate ECC processing, allowing for increased error correction capability without significantly increasing die size or processing time by optimizing the use of check bits across channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more complex error correction codes (such as DEC-TED BCH code or Reed-Solomon code) are used to correct multiple-bit errors, then error correction capability is improved, but die size increases and processing time increases
Solution Approach 1:
The patent divides the error correction functionality into multiple independent channels, each handling a portion of the data bits. Instead of using a single complex DEC-TED BCH code across all data bits, the system segments the data into multiple channels and applies simpler SEC-DED codes to each channel independently. This segmentation reduces the complexity and die size while maintaining overall error correction capability through the distributed channel structure.
2Reliability
If more complex error correction codes (such as DEC-TED BCH code or Reed-Solomon code) are used to correct multiple-bit errors, then error correction capability is improved, but processing time increases
Solution Approach 1:
By segmenting the error correction task across multiple channels that operate in parallel, the patent reduces the processing time compared to a single complex code. Each channel processes its portion of data independently and simultaneously, avoiding the sequential processing bottleneck of complex DEC-TED BCH codes while achieving equivalent or better error correction capability through the combined effect of multiple channels.
Solution Approach 2:
The patent employs flexible code-length ECC where the code length and check bit allocation can be dynamically adjusted per channel based on the specific error correction requirements. This dynamic adaptation allows the system to optimize processing time by using shorter, faster codes for channels with lower error probabilities while allocating more robust coding only where needed, thereby reducing overall processing time compared to uniformly applying complex codes.
3Device complexity
If simple ECC codes (such as SEC-DED extended-Hamming code) are used, then die size is reduced and processing time is reduced, but error correction capability is insufficient for high-precision systems
Solution Approach 1:
The patent merges multiple simple SEC-DED error correction channels to achieve the equivalent error correction capability of complex DEC-TED codes. By combining the error correction functionality across multiple channels, each using simple SEC-DED codes, the system achieves the cumulative error correction capability needed for high-precision systems while avoiding the die size and complexity overhead of implementing a single complex code.
Data Source
AI summary
Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.