Memory ECC Circuit With Syndrome-Based Multi-Bit Error Detection
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Solution Overview
Problem
Existing semiconductor memory devices struggle to accurately detect and correct multi-bit errors, as many error correction circuits are limited to correcting single-bit errors, leading to data fidelity issues during read operations.
Innovation Solution
The implementation of a multi-bit error (MBE) detection circuit within the semiconductor device, which generates syndrome bits to identify multi-bit errors, using schemes such as single error correction single error detection (SEC-SED) and single error correction double error detection (SEC-DED), and provides alerts or flags to manage error correction, including the use of additional parity bits to enhance error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction circuits are used, then single-bit errors can be corrected, but multi-bit errors cannot be detected or corrected
Solution Approach 1:
The error detection function is segmented from the traditional error correction circuit. A separate multi-bit error detection circuit is introduced that works in conjunction with the existing error correction circuit, allowing the system to handle both single-bit and multi-bit errors independently through dedicated functional modules
Solution Approach 2:
Syndrome bits serve as an intermediary mechanism between the data bits and the error detection/correction process. The syndrome bits are generated based on the data bits and parity bits, and they provide information about the presence and location of errors without directly revealing the error pattern, enabling both single-bit correction and multi-bit detection
2Reliability
If error correction circuits are added to memory devices, then data fidelity improves, but the ability to resolve multi-bit errors remains limited
Solution Approach 1:
The system performs partial error correction (single-bit) and partial error detection (multi-bit) through different circuit paths. Rather than attempting to fully correct all error types with a single circuit, the invention uses the error correction circuit for single-bit correction and the multi-bit error detection circuit for detecting uncorrectable multi-bit errors, providing comprehensive error handling through specialized partial functions
3Adaptability or versatility
If additional parity bits are used for error detection, then multi-bit error detection capability improves, but device complexity increases
Solution Approach 1:
The additional parity bits serve multiple functions: they participate in generating syndrome bits for single-bit error correction and simultaneously provide the basis for multi-bit error detection. This multi-functionality allows the same hardware structure to handle both error correction and multi-bit error detection without requiring completely separate systems
Data Source
AI summary
Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.